Collective network for computer structures
Abstract
A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to the needs of a processing algorithm.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1113767
- Patent Number(s):
- 8626957
- Application Number:
- 13/101,566
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
- DOE Contract Number:
- B517552
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2011 May 05
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Blumrich, Matthias A, Coteus, Paul W, Chen, Dong, Gara, Alan, Giampapa, Mark E, Heidelberger, Philip, Hoenicke, Dirk, Takken, Todd E, Steinmacher-Burow, Burkhard D, and Vranas, Pavlos M. Collective network for computer structures. United States: N. p., 2014.
Web.
Blumrich, Matthias A, Coteus, Paul W, Chen, Dong, Gara, Alan, Giampapa, Mark E, Heidelberger, Philip, Hoenicke, Dirk, Takken, Todd E, Steinmacher-Burow, Burkhard D, & Vranas, Pavlos M. Collective network for computer structures. United States.
Blumrich, Matthias A, Coteus, Paul W, Chen, Dong, Gara, Alan, Giampapa, Mark E, Heidelberger, Philip, Hoenicke, Dirk, Takken, Todd E, Steinmacher-Burow, Burkhard D, and Vranas, Pavlos M. Tue .
"Collective network for computer structures". United States. https://www.osti.gov/servlets/purl/1113767.
@article{osti_1113767,
title = {Collective network for computer structures},
author = {Blumrich, Matthias A and Coteus, Paul W and Chen, Dong and Gara, Alan and Giampapa, Mark E and Heidelberger, Philip and Hoenicke, Dirk and Takken, Todd E and Steinmacher-Burow, Burkhard D and Vranas, Pavlos M},
abstractNote = {A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to the needs of a processing algorithm.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {1}
}
Works referenced in this record:
Negotiation protocol for establishment of full duplex communication on a token ring network
patent, May 1995
- Yang, Henry S.; Spinney, Barry A.; Hawe, William
- US Patent Document 5,414,700
Reducing the complexities of the transmission control protocol for a high-speed networking environment
patent, August 1995
- Nguyen, Mai
- US Patent Document 5,442,637
Barrier and eureka synchronization architecture for multiprocessors
patent, February 1998
- Kessler, Richard E.; Oberlin, Steven M.; Thorson, Gregory Michael
- US Patent Document 5,721,921
Self-synchronous packet scrambler
patent, November 1998
- Lang, Steven F.
- US Patent Document 5,835,602
Multi-protocol dual fiber link laser diode controller and method
patent, September 1999
- Levinson, Frank H.; Freeman, William R.; Kane, Daniel
- US Patent Document 5,956,168
Distributed precomputation of network signal paths with table-based link capacity control
patent, February 2000
- Doshi, Bharat Tarachand; Dravida, Subrahmanyam; Harshavardhana, Paramasiviah
- US Patent Document 6,021,113
Apparatus and method for improved vector processing to support extended-length integer arithmetic
patent, September 2001
- Resnick, David R.; Moore, William T.
- US Patent Document 6,295,597
Architecture for lightweight signaling in ATM networks
patent, April 2003
- Hjalmtysson, Gisli; Ramakrishnan, Kadangode K.
- US Patent Document 6,556,577
Global interrupt and barrier networks
patent, October 2008
- Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.
- US Patent Document 7,444,385
Configuring compute nodes of a parallel computer in an operational group into a plurality of independent non-overlapping collective networks
patent, March 2010
- Archer, Charles J.; Inglett, Todd A.; Ratterman, Joseph D.
- US Patent Document 7,673,011
Interfacing apparatus and method for adapting Ethernet directly to physical channel
patent-application, November 2001
- Yu, Shaohua
- US Patent Application 09/817269; 20010043603
Method and computer program product for internet protocol (IP)-flow classification in a wireless point to multi-point (PTMP)
patent-application, April 2003
- Jorgensen, Jacob W.
- US Patent Application 10/241454; 20030067903
Global interrupt and barrier networks
patent-application, April 2004
- Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.
- US Patent Application 10/468997; 20040068599
Arithmetic functions in torus and tree networks
patent-application, April 2004
- Bhanot, Gyan; Blumrich, Matthias A.; Chen, Dong
- US Patent Application 10/468991; 20040073590
Global tree network for computing structures
patent-application, April 2004
- Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.
- US Patent Document 10/469000; 20040078493
Class network routing
patent-application, April 2004
- Bhanot, Gyan V.; Blumrich, Matthias A.; Chen, Dong
- US Patent Application 10/468999; 20040081155
Novel massively parallel supercomputer
patent-application, May 2004
- Blumrich, Matthias A.; Chen, Dong; Chiu, George L.
- US Patent Application 10/468993; 20040103218
Deterministic error recovery protocol
patent-application, April 2005
- Blumrich, Matthias A.; CHen, Dong; Gara, Alan G.
- US Patent Application 10/674952; 20050081078