Multiprocessor system with multiple concurrent modes of execution

Ahn, Daniel; Ceze, Luis H; Chen, Dong; Gara, Alan; Heidelberger, Philip; Ohmacht, Martin

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A - human necessities
A01 - agriculture
A21 - baking
A22 - butchering
A23 - foods or foodstuffs
A24 - tobacco
A41 - wearing apparel
A42 - headwear
A43 - footwear
A44 - haberdashery
A45 - hand or travelling articles
A46 - brushware
A47 - furniture
A61 - medical or veterinary science
A62 - life-saving
A63 - sports
A99 - subject matter not otherwise provided for in this section
B - performing operations
B01 - physical or chemical processes or apparatus in general
B02 - crushing, pulverising, or disintegrating
B03 - separation of solid materials using liquids or using pneumatic tables or jigs
B04 - centrifugal apparatus or machines for carrying-out physical or chemical processes
B05 - spraying or atomising in general
B06 - generating or transmitting mechanical vibrations in general
B07 - separating solids from solids
B08 - cleaning
B09 - disposal of solid waste
B21 - mechanical metal-working without essentially removing material
B22 - casting
B23 - machine tools
B24 - grinding
B25 - hand tools
B26 - hand cutting tools
B27 - working or preserving wood or similar material
B28 - working cement, clay, or stone
B29 - working of plastics
B30 - presses
B31 - making articles of paper, cardboard or material worked in a manner analogous to paper
B32 - layered products
B33 - additive manufacturing technology
B41 - printing
B42 - bookbinding
B43 - writing or drawing implements
B44 - decorative arts
B60 - vehicles in general
B61 - railways
B62 - land vehicles for travelling otherwise than on rails
B63 - ships or other waterborne vessels
B64 - aircraft
B65 - conveying
B66 - hoisting
B67 - opening, closing {or cleaning} bottles, jars or similar containers
B68 - saddlery
B81 - microstructural technology
B82 - nanotechnology
B99 - subject matter not otherwise provided for in this section
C - chemistry
C01 - inorganic chemistry
C02 - treatment of water, waste water, sewage, or sludge
C03 - glass
C04 - cements
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C09 - dyes
C10 - petroleum, gas or coke industries
C11 - animal or vegetable oils, fats, fatty substances or waxes
C12 - biochemistry
C13 - sugar industry
C14 - skins
C21 - metallurgy of iron
C22 - metallurgy
C23 - coating metallic material
C25 - electrolytic or electrophoretic processes
C30 - crystal growth
C40 - combinatorial technology
C99 - subject matter not otherwise provided for in this section
D - textiles
D01 - natural or man-made threads or fibres
D02 - yarns
D03 - weaving
D04 - braiding
D05 - sewing
D06 - treatment of textiles or the like
D07 - ropes
D10 - indexing scheme associated with sublasses of section d, relating to textiles
D21 - paper-making
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E01 - construction of roads, railways, or bridges
E02 - hydraulic engineering
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E06 - doors, windows, shutters, or roller blinds in general
E21 - earth drilling
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F - mechanical engineering
F01 - machines or engines in general
F02 - combustion engines
F03 - machines or engines for liquids
F04 - positive - displacement machines for liquids
F05 - indexing schemes relating to engines or pumps in various subclasses of classes f01-f04
F15 - fluid-pressure actuators
F16 - engineering elements and units
F17 - storing or distributing gases or liquids
F21 - lighting
F22 - steam generation
F23 - combustion apparatus
F24 - heating
F25 - refrigeration or cooling
F26 - drying
F27 - furnaces
F28 - heat exchange in general
F41 - weapons
F42 - ammunition
F99 - subject matter not otherwise provided for in this section
G - physics
G01 - measuring
G02 - optics
G03 - photography
G04 - horology
G05 - controlling
G06 - computing
G07 - checking-devices
G08 - signalling
G09 - education
G10 - musical instruments
G11 - information storage
G12 - instrument details
G16 - information and communication technology [ict] specially adapted for specific application fields
G21 - nuclear physics
G99 - subject matter not otherwise provided for in this section
H - electricity
H01 - basic electric elements
H02 - generation
H03 - basic electronic circuitry
H04 - electric communication technique
H05 - electric techniques not otherwise provided for
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Title: Multiprocessor system with multiple concurrent modes of execution

Abstract

A multiprocessor system supports multiple concurrent modes of speculative execution. Speculation identification numbers (IDs) are allocated to speculative threads from a pool of available numbers. The pool is divided into domains, with each domain being assigned to a mode of speculation. Modes of speculation include TM, TLS, and rollback. Allocation of the IDs is carried out with respect to a central state table and using hardware pointers. The IDs are used for writing different versions of speculative results in different ways of a set in a cache memory.

Inventors:: Ahn, Daniel; Ceze, Luis H; Chen, Dong; Gara, Alan; Heidelberger, Philip; Ohmacht, Martin

Issue Date:: 2013-12-31

Research Org.:: International Business Machines Corporations (Armonk, NY)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1113225

Patent Number(s):: 8621478

Application Number:: 13/008,502

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/08 - in hierarchically structured memory systems, e.g. virtual memory systems
G06F12/084 - with a shared cache
G06F12/0842 - for multiprocessing or multitasking
G06F9/524 - {Deadlock detection or avoidance}

Show less

DOE Contract Number:: B554331

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Ahn, Daniel, Ceze, Luis H, Chen, Dong, Gara, Alan, Heidelberger, Philip, and Ohmacht, Martin. Multiprocessor system with multiple concurrent modes of execution.  United States: N. p., 2013. 
        Web.

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                    Ahn, Daniel, Ceze, Luis H, Chen, Dong, Gara, Alan, Heidelberger, Philip, & Ohmacht, Martin. Multiprocessor system with multiple concurrent modes of execution.  United States.

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                    Ahn, Daniel, Ceze, Luis H, Chen, Dong, Gara, Alan, Heidelberger, Philip, and Ohmacht, Martin. Tue .  
        "Multiprocessor system with multiple concurrent modes of execution".  United States.  https://www.osti.gov/servlets/purl/1113225.

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@article{osti_1113225,

  title        = {Multiprocessor system with multiple concurrent modes of execution},

  author       = {Ahn, Daniel and Ceze, Luis H and Chen, Dong and Gara, Alan and Heidelberger, Philip and Ohmacht, Martin},

  abstractNote = {A multiprocessor system supports multiple concurrent modes of speculative execution. Speculation identification numbers (IDs) are allocated to speculative threads from a pool of available numbers. The pool is divided into domains, with each domain being assigned to a mode of speculation. Modes of speculation include TM, TLS, and rollback. Allocation of the IDs is carried out with respect to a central state table and using hardware pointers. The IDs are used for writing different versions of speculative results in different ways of a set in a cache memory.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2013},

  month        = {12}

}

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Title: Multiprocessor system with multiple concurrent modes of execution

Abstract

Citation Formats

Store Aware Prefetching for a Datastream patent-application, March 2011

Efficient Deterministic Multiprocessing patent-application, September 2009

Verification of memory consistency and transactional memory patent, October 2010

Speculative multiaddress atomicity patent, May 2008

Low complexity speculative multithreading system based on unmodified microprocessor core patent, July 2008

Method and Apparatus for Employing Multi-Bit Register File Cells and SMT Thread Groups patent-application, December 2008

System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture patent, March 2002

Detecting full conditions in a queue patent, October 2002

Apparatus and method for sparse line write transactions patent-application, February 2007

Transactional Conflict Resolution Based on Locality patent-application, January 2011

Cache way prediction based on instruction base register patent-application, September 2002

Enabling Speculative State Information in a Cache Coherency Protocol patent-application, March 2009

Processor with cache way prediction and method thereof patent-application, May 2006

Low complexity speculative multithreading system based on unmodified microprocessor core patent, November 2010

Using Time Stamps to Facilitate Load Reordering patent-application, August 2010

Stall technique to facilitate atomicity in processor execution of helper set patent-application, September 2004

Synchronization of parallel processes patent-application, September 2005

Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory patent-application, December 2008

Automated partitioning of a computation for parallel or other high capability architecture patent, November 2011

Computing System with Transactional Memory Using Millicode Assists patent-application, November 2008

Cache control device and control method patent-application, July 2010

Fast and accurate cache way selection patent-application, January 2003

Multi-thread packet processor patent-application, June 2002

Apparatus and method for preventing cache data eviction during an atomic operation patent, February 2002

Transactional memory in out-of-order processors patent, May 2012

Architectural support for thread level speculative execution patent-application, August 2007

System and Method for Executing Nested Atomic Blocks Using Split Hardware Transactions patent-application, January 2009

Separate data/coherency caches in a shared memory multiprocessor system patent-application, July 2007

Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level patent, April 2009

Snoop Filter Directory Mechanism in Coherency Shared Memory System patent-application, December 2007

Prefetch Miss Indicator for Cache Coherence Directory Misses on External Caches patent-application, August 2008

Method, System and Apparatus for Reducing Memory Traffic in a Distributed Memory System patent-application, November 2009

Eviction override for larx-reserved addresses patent, April 2001

Safe store for speculative helper threads patent, February 2010

System and Method for Handling Overflow in Hardware Transactional Memory with Locks patent-application, July 2009

Enabling speculative state information in a cache coherency protocol patent, May 2012

Hierarchical Bloom Filters for Facilitating Concurrency Control patent-application, December 2010

Strand-Based Computing Hardware and Dynamically Optimizing Strandware for a High Performance Microprocessor System patent-application, June 2009

Processor associated blocking symbol controls for serializing the accessing of data resources in a computer system patent, April 1999

Implementation of load linked and store conditional operations patent-application, July 2006

Store Aware Prefetching for a Datastream
patent-application, March 2011

Efficient Deterministic Multiprocessing
patent-application, September 2009

Verification of memory consistency and transactional memory
patent, October 2010

Speculative multiaddress atomicity
patent, May 2008

Low complexity speculative multithreading system based on unmodified microprocessor core
patent, July 2008

Method and Apparatus for Employing Multi-Bit Register File Cells and SMT Thread Groups
patent-application, December 2008

System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture
patent, March 2002

Detecting full conditions in a queue
patent, October 2002

Apparatus and method for sparse line write transactions
patent-application, February 2007

Transactional Conflict Resolution Based on Locality
patent-application, January 2011

Cache way prediction based on instruction base register
patent-application, September 2002

Enabling Speculative State Information in a Cache Coherency Protocol
patent-application, March 2009

Processor with cache way prediction and method thereof
patent-application, May 2006

Low complexity speculative multithreading system based on unmodified microprocessor core
patent, November 2010

Using Time Stamps to Facilitate Load Reordering
patent-application, August 2010

Stall technique to facilitate atomicity in processor execution of helper set
patent-application, September 2004

Synchronization of parallel processes
patent-application, September 2005

Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory
patent-application, December 2008

Automated partitioning of a computation for parallel or other high capability architecture
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Computing System with Transactional Memory Using Millicode Assists
patent-application, November 2008

Cache control device and control method
patent-application, July 2010

Fast and accurate cache way selection
patent-application, January 2003

Multi-thread packet processor
patent-application, June 2002

Apparatus and method for preventing cache data eviction during an atomic operation
patent, February 2002

Transactional memory in out-of-order processors
patent, May 2012

Architectural support for thread level speculative execution
patent-application, August 2007

System and Method for Executing Nested Atomic Blocks Using Split Hardware Transactions
patent-application, January 2009

Separate data/coherency caches in a shared memory multiprocessor system
patent-application, July 2007

Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level
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Snoop Filter Directory Mechanism in Coherency Shared Memory System
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Prefetch Miss Indicator for Cache Coherence Directory Misses on External Caches
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Method, System and Apparatus for Reducing Memory Traffic in a Distributed Memory System
patent-application, November 2009

Eviction override for larx-reserved addresses
patent, April 2001

Safe store for speculative helper threads
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System and Method for Handling Overflow in Hardware Transactional Memory with Locks
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Enabling speculative state information in a cache coherency protocol
patent, May 2012

Hierarchical Bloom Filters for Facilitating Concurrency Control
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Strand-Based Computing Hardware and Dynamically Optimizing Strandware for a High Performance Microprocessor System
patent-application, June 2009

Processor associated blocking symbol controls for serializing the accessing of data resources in a computer system
patent, April 1999

Implementation of load linked and store conditional operations
patent-application, July 2006