Wafer-level packaging with compression-controlled seal ring bonding
Abstract
A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1107804
- Patent Number(s):
- 8575748
- Application Number:
- 13/324,076
- Assignee:
- Sandia Corporation (Albuquerque, NM)
- Patent Classifications (CPCs):
-
B - PERFORMING OPERATIONS B81 - MICROSTRUCTURAL TECHNOLOGY B81B - MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
B - PERFORMING OPERATIONS B81 - MICROSTRUCTURAL TECHNOLOGY B81C - PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- DOE Contract Number:
- AC04-94AL85000
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING
Citation Formats
Farino, Anthony J. Wafer-level packaging with compression-controlled seal ring bonding. United States: N. p., 2013.
Web.
Farino, Anthony J. Wafer-level packaging with compression-controlled seal ring bonding. United States.
Farino, Anthony J. Tue .
"Wafer-level packaging with compression-controlled seal ring bonding". United States. https://www.osti.gov/servlets/purl/1107804.
@article{osti_1107804,
title = {Wafer-level packaging with compression-controlled seal ring bonding},
author = {Farino, Anthony J},
abstractNote = {A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2013},
month = {11}
}
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Works referenced in this record:
Wafer level packaging using flip chip mounting
patent, December 2012
- Tabrizi, Behnam
- US Patent Document 8,324,728