Title: Matrix multiplication operations with data pre-conditioning in a high performance computing architecture

Abstract

Mechanisms for performing matrix multiplication operations with data pre-conditioning in a high performance computing architecture are provided. A vector load operation is performed to load a first vector operand of the matrix multiplication operation to a first target vector register. A load and splat operation is performed to load an element of a second vector operand and replicating the element to each of a plurality of elements of a second target vector register. A multiply add operation is performed on elements of the first target vector register and elements of the second target vector register to generate a partial product of the matrix multiplication operation. The partial product of the matrix multiplication operation is accumulated with other partial products of the matrix multiplication operation.

Inventors:

Eichenberger, Alexandre E; Gschwind, Michael K; Gunnels, John A

Issue Date:

2013-11-05

Research Org.:

International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1107797

Patent Number(s):

8577950

Application Number:

12/542,255

Assignee:

International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F17/16 - Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
G06F9/30014 - {with variable precision}
G06F9/30029 - {Logical and Boolean instructions, e.g. XOR, NOT}
G06F9/30032 - {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE}
G06F9/30036 - {Instructions to perform operations on packed data, e.g. vector operations}
G06F9/30043 - {LOAD or STORE instructions
G06F9/30072 - {to perform conditional operations, e.g. using guard}
G06F9/30094 - {Condition code generation, e.g. Carry, Zero flag}
G06F9/30109 - {having multiple operands in a single register}
G06F9/3013 - {according to data content, e.g. floating-point registers, address registers}
G06F9/3885 - {using a plurality of independent parallel functional units}
G06F9/3887 - {controlled by a single instruction, e.g. SIMD}

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DOE Contract Number:  

B554331

Resource Type:

Patent

Country of Publication:

United States

Language:

English

Subject:

97 MATHEMATICS AND COMPUTING