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Title: Method of data communications with reduced latency

Abstract

Data communications with reduced latency, including: writing, by a producer, a descriptor and message data into at least two descriptor slots of a descriptor buffer, the descriptor buffer comprising allocated computer memory segmented into descriptor slots, each descriptor slot having a fixed size, the descriptor buffer having a header pointer that identifies a next descriptor slot to be processed by a DMA controller, the descriptor buffer having a tail pointer that identifies a descriptor slot for entry of a next descriptor in the descriptor buffer; recording, by the producer, in the descriptor a value signifying that message data has been written into descriptor slots; and setting, by the producer, in dependence upon the recorded value, a tail pointer to point to a next open descriptor slot.

Inventors:
;
Issue Date:
Research Org.:
International Business Machines Corporation (Armonk, NY)
Sponsoring Org.:
USDOE
OSTI Identifier:
1107795
Patent Number(s):
8,578,068
Application Number:
12/947,520
Assignee:
International Business Machines Corporation (Armonk, NY)
DOE Contract Number:  
B544331
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Blocksome, Michael A, and Parker, Jeffrey J. Method of data communications with reduced latency. United States: N. p., 2013. Web.
Blocksome, Michael A, & Parker, Jeffrey J. Method of data communications with reduced latency. United States.
Blocksome, Michael A, and Parker, Jeffrey J. Tue . "Method of data communications with reduced latency". United States. https://www.osti.gov/servlets/purl/1107795.
@article{osti_1107795,
title = {Method of data communications with reduced latency},
author = {Blocksome, Michael A and Parker, Jeffrey J},
abstractNote = {Data communications with reduced latency, including: writing, by a producer, a descriptor and message data into at least two descriptor slots of a descriptor buffer, the descriptor buffer comprising allocated computer memory segmented into descriptor slots, each descriptor slot having a fixed size, the descriptor buffer having a header pointer that identifies a next descriptor slot to be processed by a DMA controller, the descriptor buffer having a tail pointer that identifies a descriptor slot for entry of a next descriptor in the descriptor buffer; recording, by the producer, in the descriptor a value signifying that message data has been written into descriptor slots; and setting, by the producer, in dependence upon the recorded value, a tail pointer to point to a next open descriptor slot.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2013},
month = {11}
}

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