Optimized scalar promotion with load and splat SIMD instructions

Eichenberger, Alexander E; Gschwind, Michael K; Gunnels, John A

Title: Optimized scalar promotion with load and splat SIMD instructions

Full Record
Other Related Research

Abstract

Mechanisms for optimizing scalar code executed on a single instruction multiple data (SIMD) engine are provided. Placement of vector operation-splat operations may be determined based on an identification of scalar and SIMD operations in an original code representation. The original code representation may be modified to insert the vector operation-splat operations based on the determined placement of vector operation-splat operations to generate a first modified code representation. Placement of separate splat operations may be determined based on identification of scalar and SIMD operations in the first modified code representation. The first modified code representation may be modified to insert or delete separate splat operations based on the determined placement of the separate splat operations to generate a second modified code representation. SIMD code may be output based on the second modified code representation for execution by the SIMD engine.

Inventors:: Eichenberger, Alexander E; Gschwind, Michael K; Gunnels, John A

Issue Date:: 2013-10-29

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1107622

Patent Number(s):: 8572586

Application Number:: 13/555,435

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F8/45 - {Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions}

Show less

DOE Contract Number:: B554331

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Eichenberger, Alexander E, Gschwind, Michael K, and Gunnels, John A. Optimized scalar promotion with load and splat SIMD instructions.  United States: N. p., 2013. 
        Web.

Copy to clipboard


                    Eichenberger, Alexander E, Gschwind, Michael K, & Gunnels, John A. Optimized scalar promotion with load and splat SIMD instructions.  United States.

Copy to clipboard


                    Eichenberger, Alexander E, Gschwind, Michael K, and Gunnels, John A. Tue .  
        "Optimized scalar promotion with load and splat SIMD instructions".  United States.  https://www.osti.gov/servlets/purl/1107622.

Copy to clipboard


                    
@article{osti_1107622,

  title        = {Optimized scalar promotion with load and splat SIMD instructions},

  author       = {Eichenberger, Alexander E and Gschwind, Michael K and Gunnels, John A},

  abstractNote = {Mechanisms for optimizing scalar code executed on a single instruction multiple data (SIMD) engine are provided. Placement of vector operation-splat operations may be determined based on an identification of scalar and SIMD operations in an original code representation. The original code representation may be modified to insert the vector operation-splat operations based on the determined placement of vector operation-splat operations to generate a first modified code representation. Placement of separate splat operations may be determined based on identification of scalar and SIMD operations in the first modified code representation. The first modified code representation may be modified to insert or delete separate splat operations based on the determined placement of the separate splat operations to generate a second modified code representation. SIMD code may be output based on the second modified code representation for execution by the SIMD engine.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2013},

  month        = {10}

}

Copy to clipboard

Patent:

Save / Share:

Export Metadata

Save to My Library

Similar Records in DOE Patents and OSTI.GOV collections:

Insertion of operation-and-indicate instructions for optimized SIMD code

Patent Eichenberger, Alexander E; Gara, Alan; Gschwind, Michael K

Mechanisms are provided for inserting indicated instructions for tracking and indicating exceptions in the execution of vectorized code. A portion of first code is received for compilation. The portion of first code is analyzed to identify non-speculative instructions performing designated non-speculative operations in the first code that are candidates for replacement by replacement operation-and-indicate instructions that perform the designated non-speculative operations and further perform an indication operation for indicating any exception conditions corresponding to special exception values present in vector register inputs to the replacement operation-and-indicate instructions. The replacement is performed and second code is generated based on the replacementmore » « less
Full Text Available
Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations

Patent Gschwind, Michael K [Chappaqua, NY]

Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the execution unit. The execution unit has logic that implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA). The floating point vector registers of the vector register file store both scalar and floating point values as vectors having a plurality of vector elements. The processor may be part of a data processing system.
Full Text Available
Matrix multiplication operations using pair-wise load and splat operations

Patent Eichenberger, Alexandre E.; Gschwind, Michael K.; Gunnels, John A.; ...

Mechanisms for performing a matrix multiplication operation are provided. A vector load operation is performed to load a first vector operand of the matrix multiplication operation to a first target vector register. A pair-wise load and splat operation is performed to load a pair of scalar values of a second vector operand and replicate the pair of scalar values within a second target vector register. An operation is performed on elements of the first target vector register and elements of the second target vector register to generate a partial product of the matrix multiplication operation. The partial product is accumulatedmore » « less
Full Text Available
Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution

Patent Fleischer, Bruce M.; Fox, Thomas Winters; Jacob, Arpith C.; ...

A processor core includes a storage device which stores a composite very large instruction word (VLIW) instruction, an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform, and a composite VLIW instruction execution unit which executes the decoded composite VLIW instruction to perform the operation.
Full Text Available
Optimizing branch re-wiring in a software instruction cache

Patent Bertolli, Carlo; O'Brien, John Kevin Patrick; Eichenberger, Alexandre E.; ...

A method includes a computer device receiving a branch instruction; the computer device managing two tables, where a first table relates to application blocks and a second table relates to available address slots; and the computer device calculating a target of the branch instruction using a branch-to-link register, the computer device optimizes re-wiring in a cache using the calculation and the managed two tables.
Full Text Available

Similar Records