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Title: Distributed trace using central performance counter memory

Abstract

A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.

Inventors:
;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1107594
Patent Number(s):
8566484
Application Number:
13/590,879
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
DOE Contract Number:  
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 0012 Aug 21
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Satterfield, David L., and Sexton, James C. Distributed trace using central performance counter memory. United States: N. p., 2013. Web.
Satterfield, David L., & Sexton, James C. Distributed trace using central performance counter memory. United States.
Satterfield, David L., and Sexton, James C. Tue . "Distributed trace using central performance counter memory". United States. https://www.osti.gov/servlets/purl/1107594.
@article{osti_1107594,
title = {Distributed trace using central performance counter memory},
author = {Satterfield, David L. and Sexton, James C.},
abstractNote = {A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2013},
month = {10}
}

Patent:

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