Cache directory look-up re-use as conflict check mechanism for speculative memory requests

Ohmacht, Martin

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Title: Cache directory look-up re-use as conflict check mechanism for speculative memory requests

Abstract

In a cache memory, energy and other efficiencies can be realized by saving a result of a cache directory lookup for sequential accesses to a same memory address. Where the cache is a point of coherence for speculative execution in a multiprocessor system, with directory lookups serving as the point of conflict detection, such saving becomes particularly advantageous.

Inventors:: Ohmacht, Martin

Issue Date:: 2013-09-10

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1093237

Patent Number(s):: 8533399

Application Number:: 12/984,252

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/0815 - Cache consistency protocols
G06F9/30043 - {LOAD or STORE instructions
G06F9/30072 - {to perform conditional operations, e.g. using guard}
G06F9/30087 - {Synchronisation or serialisation instructions}
G06F9/3834 - {Maintaining memory consistency

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
Y02D10/00 - Energy efficient computing

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DOE Contract Number:: B554331

Resource Type:: Patent

Resource Relation:: Patent File Date: 2011 Jan 04

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Ohmacht, Martin. Cache directory look-up re-use as conflict check mechanism for speculative memory requests.  United States: N. p., 2013. 
        Web.

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                    Ohmacht, Martin. Cache directory look-up re-use as conflict check mechanism for speculative memory requests.  United States.

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                    Ohmacht, Martin. Tue .  
        "Cache directory look-up re-use as conflict check mechanism for speculative memory requests".  United States.  https://www.osti.gov/servlets/purl/1093237.

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@article{osti_1093237,

  title        = {Cache directory look-up re-use as conflict check mechanism for speculative memory requests},

  author       = {Ohmacht, Martin},

  abstractNote = {In a cache memory, energy and other efficiencies can be realized by saving a result of a cache directory lookup for sequential accesses to a same memory address. Where the cache is a point of coherence for speculative execution in a multiprocessor system, with directory lookups serving as the point of conflict detection, such saving becomes particularly advantageous.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2013},

  month        = {9}

}

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Similar Records

Title: Cache directory look-up re-use as conflict check mechanism for speculative memory requests

Abstract

Citation Formats

Store Aware Prefetching for a Datastream patent-application, March 2011

Efficient Deterministic Multiprocessing patent-application, September 2009

Method and Apparatus for Employing Multi-Bit Register File Cells and SMT Thread Groups patent-application, December 2008

System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture patent, March 2002

Detecting full conditions in a queue patent, October 2002

Apparatus and method for sparse line write transactions patent-application, February 2007

Cache way prediction based on instruction base register patent-application, September 2002

Enabling Speculative State Information in a Cache Coherency Protocol patent-application, March 2009

Processor with cache way prediction and method thereof patent-application, May 2006

Using Time Stamps to Facilitate Load Reordering patent-application, August 2010

Stall technique to facilitate atomicity in processor execution of helper set patent-application, September 2004

Synchronization of parallel processes patent-application, September 2005

Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory patent-application, December 2008

Cache control device and control method patent-application, July 2010

Fast and accurate cache way selection patent-application, January 2003

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Snoop Filter Directory Mechanism in Coherency Shared Memory System patent-application, December 2007

Prefetch Miss Indicator for Cache Coherence Directory Misses on External Caches patent-application, August 2008

Method, System and Apparatus for Reducing Memory Traffic in a Distributed Memory System patent-application, November 2009

Eviction override for larx-reserved addresses patent, April 2001

Hierarchical Bloom Filters for Facilitating Concurrency Control patent-application, December 2010

Processor associated blocking symbol controls for serializing the accessing of data resources in a computer system patent, April 1999

Implementation of load linked and store conditional operations patent-application, July 2006

Store Aware Prefetching for a Datastream
patent-application, March 2011

Efficient Deterministic Multiprocessing
patent-application, September 2009

Method and Apparatus for Employing Multi-Bit Register File Cells and SMT Thread Groups
patent-application, December 2008

System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture
patent, March 2002

Detecting full conditions in a queue
patent, October 2002

Apparatus and method for sparse line write transactions
patent-application, February 2007

Cache way prediction based on instruction base register
patent-application, September 2002

Enabling Speculative State Information in a Cache Coherency Protocol
patent-application, March 2009

Processor with cache way prediction and method thereof
patent-application, May 2006

Using Time Stamps to Facilitate Load Reordering
patent-application, August 2010

Stall technique to facilitate atomicity in processor execution of helper set
patent-application, September 2004

Synchronization of parallel processes
patent-application, September 2005

Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory
patent-application, December 2008

Cache control device and control method
patent-application, July 2010

Fast and accurate cache way selection
patent-application, January 2003

Multi-thread packet processor
patent-application, June 2002

Apparatus and method for preventing cache data eviction during an atomic operation
patent, February 2002

Architectural support for thread level speculative execution
patent-application, August 2007

System and Method for Executing Nested Atomic Blocks Using Split Hardware Transactions
patent-application, January 2009

Separate data/coherency caches in a shared memory multiprocessor system
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patent-application, December 2007

Prefetch Miss Indicator for Cache Coherence Directory Misses on External Caches
patent-application, August 2008

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Eviction override for larx-reserved addresses
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Hierarchical Bloom Filters for Facilitating Concurrency Control
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Processor associated blocking symbol controls for serializing the accessing of data resources in a computer system
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