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Title: Growth of coincident site lattice matched semiconductor layers and devices on crystalline substrates

Abstract

Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a') that is related to the substrate lattice parameter (a). The lattice parameter (a') maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.

Inventors:
;
Issue Date:
Research Org.:
National Renewable Energy Lab. (NREL), Golden, CO (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1092976
Patent Number(s):
8,507,365
Application Number:
12/643,127
Assignee:
Alliance for Sustainable Energy, LLC (Golden, CO)
DOE Contract Number:  
AC36-08GO28308
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE

Citation Formats

Norman, Andrew G, and Ptak, Aaron J. Growth of coincident site lattice matched semiconductor layers and devices on crystalline substrates. United States: N. p., 2013. Web.
Norman, Andrew G, & Ptak, Aaron J. Growth of coincident site lattice matched semiconductor layers and devices on crystalline substrates. United States.
Norman, Andrew G, and Ptak, Aaron J. Tue . "Growth of coincident site lattice matched semiconductor layers and devices on crystalline substrates". United States. https://www.osti.gov/servlets/purl/1092976.
@article{osti_1092976,
title = {Growth of coincident site lattice matched semiconductor layers and devices on crystalline substrates},
author = {Norman, Andrew G and Ptak, Aaron J},
abstractNote = {Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a') that is related to the substrate lattice parameter (a). The lattice parameter (a') maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2013},
month = {8}
}

Patent:

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