Ordering of guarded and unguarded stores for no-sync I/O
Abstract
A parallel computing system processes at least one store instruction. A first processor core issues a store instruction. A first queue, associated with the first processor core, stores the store instruction. A second queue, associated with a first local cache memory device of the first processor core, stores the store instruction. The first processor core updates first data in the first local cache memory device according to the store instruction. The third queue, associated with at least one shared cache memory device, stores the store instruction. The first processor core invalidates second data, associated with the store instruction, in the at least one shared cache memory. The first processor core invalidates third data, associated with the store instruction, in other local cache memory devices of other processor cores. The first processor core flushing only the first queue.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1086942
- Patent Number(s):
- 8473683
- Application Number:
- 12/986,349
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- B554331
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Gara, Alan, and Ohmacht, Martin. Ordering of guarded and unguarded stores for no-sync I/O. United States: N. p., 2013.
Web.
Gara, Alan, & Ohmacht, Martin. Ordering of guarded and unguarded stores for no-sync I/O. United States.
Gara, Alan, and Ohmacht, Martin. Tue .
"Ordering of guarded and unguarded stores for no-sync I/O". United States. https://www.osti.gov/servlets/purl/1086942.
@article{osti_1086942,
title = {Ordering of guarded and unguarded stores for no-sync I/O},
author = {Gara, Alan and Ohmacht, Martin},
abstractNote = {A parallel computing system processes at least one store instruction. A first processor core issues a store instruction. A first queue, associated with the first processor core, stores the store instruction. A second queue, associated with a first local cache memory device of the first processor core, stores the store instruction. The first processor core updates first data in the first local cache memory device according to the store instruction. The third queue, associated with at least one shared cache memory device, stores the store instruction. The first processor core invalidates second data, associated with the store instruction, in the at least one shared cache memory. The first processor core invalidates third data, associated with the store instruction, in other local cache memory devices of other processor cores. The first processor core flushing only the first queue.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2013},
month = {6}
}
Works referenced in this record:
Aggressive Store Merging in a Processor that Supports Checkpointing
patent-application, December 2009
- Caprioli, Paul; Karlsson, Martin; Levinsky, Gideon N.
- US Patent Application 12/128332; 20090300338
Synchronous message queues
patent, July 2007
- Ogasawara, Gary Hayato; Schwartz, Jonah; Stone, David
- US Patent Document 7,249,229