Insertion of operation-and-indicate instructions for optimized SIMD code

Eichenberger, Alexander E; Gara, Alan; Gschwind, Michael K

Title: Insertion of operation-and-indicate instructions for optimized SIMD code

Abstract

Mechanisms are provided for inserting indicated instructions for tracking and indicating exceptions in the execution of vectorized code. A portion of first code is received for compilation. The portion of first code is analyzed to identify non-speculative instructions performing designated non-speculative operations in the first code that are candidates for replacement by replacement operation-and-indicate instructions that perform the designated non-speculative operations and further perform an indication operation for indicating any exception conditions corresponding to special exception values present in vector register inputs to the replacement operation-and-indicate instructions. The replacement is performed and second code is generated based on the replacement of the at least one non-speculative instruction. The data processing system executing the compiled code is configured to store special exception values in vector output registers, in response to a speculative instruction generating an exception condition, without initiating exception handling.

Inventors:: Eichenberger, Alexander E; Gara, Alan; Gschwind, Michael K

Issue Date:: 2013-06-04

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1084334

Patent Number(s):: 8458684

Application Number:: 12/543,628

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F8/451 - {Code distribution
G06F9/30007 - {to perform operations on data operands}
G06F9/30021 - {Compare instructions, e.g. Greater-Than, Equal-To, MINMAX}
G06F9/30036 - {Instructions to perform operations on packed data, e.g. vector operations}
G06F9/30043 - {LOAD or STORE instructions
G06F9/3865 - {using deferred exception handling, e.g. exception flags}
G06F9/3887 - {controlled by a single instruction, e.g. SIMD}

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DOE Contract Number:: B554331

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Eichenberger, Alexander E, Gara, Alan, and Gschwind, Michael K. Insertion of operation-and-indicate instructions for optimized SIMD code.  United States: N. p., 2013. 
        Web.

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                    Eichenberger, Alexander E, Gara, Alan, & Gschwind, Michael K. Insertion of operation-and-indicate instructions for optimized SIMD code.  United States.

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                    Eichenberger, Alexander E, Gara, Alan, and Gschwind, Michael K. Tue .  
        "Insertion of operation-and-indicate instructions for optimized SIMD code".  United States.  https://www.osti.gov/servlets/purl/1084334.

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@article{osti_1084334,

  title        = {Insertion of operation-and-indicate instructions for optimized SIMD code},

  author       = {Eichenberger, Alexander E and Gara, Alan and Gschwind, Michael K},

  abstractNote = {Mechanisms are provided for inserting indicated instructions for tracking and indicating exceptions in the execution of vectorized code. A portion of first code is received for compilation. The portion of first code is analyzed to identify non-speculative instructions performing designated non-speculative operations in the first code that are candidates for replacement by replacement operation-and-indicate instructions that perform the designated non-speculative operations and further perform an indication operation for indicating any exception conditions corresponding to special exception values present in vector register inputs to the replacement operation-and-indicate instructions. The replacement is performed and second code is generated based on the replacement of the at least one non-speculative instruction. The data processing system executing the compiled code is configured to store special exception values in vector output registers, in response to a speculative instruction generating an exception condition, without initiating exception handling.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2013},

  month        = {6}

}

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Similar Records

Title: Insertion of operation-and-indicate instructions for optimized SIMD code

Abstract

Citation Formats

System for handling load errors having symbolic entity generator to generate symbolic entity and ALU to propagate the symbolic entity patent, February 2003

Method and system for supporting speculative execution using a speculative look-aside table patent, May 1998

Handling of exceptions in speculative instructions patent, August 1998

Register substitution during exception processing patent, January 1995

Computer architecture for the deferral of exceptions on speculative instructions patent, June 1999

Method and apparatus for dynamic scheduling of instructions to ensure sequentially coherent data in a processor employing out-of-order execution patent, August 1997

Method for parking a vehicle patent, July 2007

Processor structure and method for tracking floating-point exceptions patent, September 1997

Floating point multiplier capable of easily performing a failure detection test patent, July 1995

Data processing method and device patent-application, March 2007

The IBM System/370 vector architecture journal, January 1986

Exception masking in binary translation patent, February 2006

Exploiting Workload Parallelism for Performance and Power Optimization in Blue Gene journal, September 2006

System and method for deferring exceptions generated during speculative execution patent, October 2001

Synergistic Processing in Cell's Multicore Architecture journal, March 2006

Processor structure and method for maintaining and restoring precise state at any instruction boundary patent, July 1997

Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations patent, July 1998

Structure and method for instruction boundary machine state restoration patent, October 1999

System for handling load errors having symbolic entity generator to generate symbolic entity and ALU to propagate the symbolic entity
patent, February 2003

Method and system for supporting speculative execution using a speculative look-aside table
patent, May 1998

Handling of exceptions in speculative instructions
patent, August 1998

Register substitution during exception processing
patent, January 1995

Computer architecture for the deferral of exceptions on speculative instructions
patent, June 1999

Method and apparatus for dynamic scheduling of instructions to ensure sequentially coherent data in a processor employing out-of-order execution
patent, August 1997

Method for parking a vehicle
patent, July 2007

Processor structure and method for tracking floating-point exceptions
patent, September 1997

Floating point multiplier capable of easily performing a failure detection test
patent, July 1995

Data processing method and device
patent-application, March 2007

The IBM System/370 vector architecture
journal, January 1986

Exception masking in binary translation
patent, February 2006

Exploiting Workload Parallelism for Performance and Power Optimization in Blue Gene
journal, September 2006

System and method for deferring exceptions generated during speculative execution
patent, October 2001

Synergistic Processing in Cell's Multicore Architecture
journal, March 2006

Processor structure and method for maintaining and restoring precise state at any instruction boundary
patent, July 1997

Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations
patent, July 1998

Structure and method for instruction boundary machine state restoration
patent, October 1999