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Title: Error detection method

Abstract

An apparatus, program product, and method that run an algorithm on a hardware based processor, generate a hardware error as a result of running the algorithm, generate an algorithm output for the algorithm, compare the algorithm output to another output for the algorithm, and detect the hardware error from the comparison. The algorithm is designed to cause the hardware based processor to heat to a degree that increases the likelihood of hardware errors to manifest, and the hardware error is observable in the algorithm output. As such, electronic components may be sufficiently heated and/or sufficiently stressed to create better conditions for generating hardware errors, and the output of the algorithm may be compared at the end of the run to detect a hardware error that occurred anywhere during the run that may otherwise not be detected by traditional methodologies (e.g., due to cooling, insufficient heat and/or stress, etc.).

Inventors:
Issue Date:
Research Org.:
NVO (Nevada Field Office, Las Vegas, NV (United States))
Sponsoring Org.:
USDOE
OSTI Identifier:
1084198
Patent Number(s):
8464143
Application Number:
12/657,025
Assignee:
Board of Regents of the Nevada System of Higher Education (Reno, NV)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
DMS-9902360
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING

Citation Formats

Olson, Eric J. Error detection method. United States: N. p., 2013. Web.
Olson, Eric J. Error detection method. United States.
Olson, Eric J. Tue . "Error detection method". United States. https://www.osti.gov/servlets/purl/1084198.
@article{osti_1084198,
title = {Error detection method},
author = {Olson, Eric J.},
abstractNote = {An apparatus, program product, and method that run an algorithm on a hardware based processor, generate a hardware error as a result of running the algorithm, generate an algorithm output for the algorithm, compare the algorithm output to another output for the algorithm, and detect the hardware error from the comparison. The algorithm is designed to cause the hardware based processor to heat to a degree that increases the likelihood of hardware errors to manifest, and the hardware error is observable in the algorithm output. As such, electronic components may be sufficiently heated and/or sufficiently stressed to create better conditions for generating hardware errors, and the output of the algorithm may be compared at the end of the run to detect a hardware error that occurred anywhere during the run that may otherwise not be detected by traditional methodologies (e.g., due to cooling, insufficient heat and/or stress, etc.).},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2013},
month = {6}
}

Works referenced in this record:

Determining modes and Grashof number in 2D turbulence: a numerical case study
journal, July 2008


Using memory errors to attack a virtual machine
conference, January 2003