Error detection method
Abstract
An apparatus, program product, and method that run an algorithm on a hardware based processor, generate a hardware error as a result of running the algorithm, generate an algorithm output for the algorithm, compare the algorithm output to another output for the algorithm, and detect the hardware error from the comparison. The algorithm is designed to cause the hardware based processor to heat to a degree that increases the likelihood of hardware errors to manifest, and the hardware error is observable in the algorithm output. As such, electronic components may be sufficiently heated and/or sufficiently stressed to create better conditions for generating hardware errors, and the output of the algorithm may be compared at the end of the run to detect a hardware error that occurred anywhere during the run that may otherwise not be detected by traditional methodologies (e.g., due to cooling, insufficient heat and/or stress, etc.).
- Inventors:
- Issue Date:
- Research Org.:
- NVO (Nevada Field Office, Las Vegas, NV (United States))
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1084198
- Patent Number(s):
- 8464143
- Application Number:
- 12/657,025
- Assignee:
- Board of Regents of the Nevada System of Higher Education (Reno, NV)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- DMS-9902360
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING
Citation Formats
Olson, Eric J. Error detection method. United States: N. p., 2013.
Web.
Olson, Eric J. Error detection method. United States.
Olson, Eric J. Tue .
"Error detection method". United States. https://www.osti.gov/servlets/purl/1084198.
@article{osti_1084198,
title = {Error detection method},
author = {Olson, Eric J.},
abstractNote = {An apparatus, program product, and method that run an algorithm on a hardware based processor, generate a hardware error as a result of running the algorithm, generate an algorithm output for the algorithm, compare the algorithm output to another output for the algorithm, and detect the hardware error from the comparison. The algorithm is designed to cause the hardware based processor to heat to a degree that increases the likelihood of hardware errors to manifest, and the hardware error is observable in the algorithm output. As such, electronic components may be sufficiently heated and/or sufficiently stressed to create better conditions for generating hardware errors, and the output of the algorithm may be compared at the end of the run to detect a hardware error that occurred anywhere during the run that may otherwise not be detected by traditional methodologies (e.g., due to cooling, insufficient heat and/or stress, etc.).},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Jun 11 00:00:00 EDT 2013},
month = {Tue Jun 11 00:00:00 EDT 2013}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.
Works referenced in this record:
Tester with driver/sensor circuit having programmable termination devices
patent, September 1979
- Fulks, Robert G.; Anderson, Robert E.
- US Patent Document 4,168,796
Process measuring device with expanded hardware error detection
patent, April 2010
- Lalla, Robert; Humpert, Axel; Gesser, Jean Luc
- US Patent Document 7,698,609
Image forming system with task scheduling and executing back on program and control poriority status of malfunction performance and execution
patent, March 1996
- Hosaka, Masao; Kimura, Yoshimasa; Sakamaki, Hisashi
- US Patent Document 5,499,370
Method and apparatus for isolating faults in a logic circuit
patent, March 1980
- Fulks, Robert G.; Enfield, Robert E.; Sacher, Eric
- US Patent Document 4,194,113
Obstacle detection system for automatically controlled elevator doors
patent, March 1988
- Baumgartner, Max
- US Patent Document 4,732,238
Performance analysis of distributed applications using automatic classification of communication inefficiencies
patent, February 2005
- Vetter, Jeffrey S.
- US Patent Document 6,850,920
System and method for logging disk failure analysis in disk nonvolatile memory
patent, November 2007
- Coatney, Douglas W.; Gillette, Scott D.
- US Patent Document 7,293,203
Data processing apparatus which operates in a plurality of operation modes and includes first and second monitoring means
patent, December 1997
- Hosaka, Masao; Kimura, Yoshimasa; Sakamaki, Hisashi
- US Patent Document 5,701,481
Method and apparatus for determining the failing operation of a device-under-test
patent, August 2006
- Martin-de-Nicolas, Pedro; Meissner, Charles Leverett; Saunders, Michael T.
- US Patent Document 7,085,980
Determining modes and Grashof number in 2D turbulence: a numerical case study
journal, July 2008
- Olson, Eric; Titi, Edriss S.
- Theoretical and Computational Fluid Dynamics, Vol. 22, Issue 5
On the smallest scale for the incompressible Navier-Stokes equations
journal, March 1989
- Henshaw, W. D.; Kreiss, H. O.; Reyna, L. G.
- Theoretical and Computational Fluid Dynamics, Vol. 1, Issue 2
Error management
patent, December 2007
- Vecoven, Frederic Louis Ghislain Gabriel; Panicker, Sundeep
- US Patent Document 7,313,717
Using memory errors to attack a virtual machine
conference, January 2003
- Govindavajhala, S.; Appel, A. W.
- 2003 Symposium on Security and Privacy, Proceedings 19th International Conference on Data Engineering (Cat. No.03CH37405)