Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition
Abstract
A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1083955
- Patent Number(s):
- 8447960
- Application Number:
- 12/684,860
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- B554331
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Chen, Dong, Giampapa, Mark, Heidelberger, Philip, Ohmacht, Martin, Satterfield, David L, Steinmacher-Burow, Burkhard, and Sugavanam, Krishnan. Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition. United States: N. p., 2013.
Web.
Chen, Dong, Giampapa, Mark, Heidelberger, Philip, Ohmacht, Martin, Satterfield, David L, Steinmacher-Burow, Burkhard, & Sugavanam, Krishnan. Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition. United States.
Chen, Dong, Giampapa, Mark, Heidelberger, Philip, Ohmacht, Martin, Satterfield, David L, Steinmacher-Burow, Burkhard, and Sugavanam, Krishnan. Tue .
"Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition". United States. https://www.osti.gov/servlets/purl/1083955.
@article{osti_1083955,
title = {Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition},
author = {Chen, Dong and Giampapa, Mark and Heidelberger, Philip and Ohmacht, Martin and Satterfield, David L and Steinmacher-Burow, Burkhard and Sugavanam, Krishnan},
abstractNote = {A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue May 21 00:00:00 EDT 2013},
month = {Tue May 21 00:00:00 EDT 2013}
}
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Works referenced in this record:
System, method, and computer program product for conditionally suspending issuing instructions of a thread
patent, March 2010
- Kissell, Kevin D.
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Executing multiple threads in a processor
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- Lewis, Russell Lee
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Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor
patent, November 2009
- May, Michael David; Hedinger, Peter; Dixon, Alastair
- US Patent Document 7,613,909