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Title: Arbitration in crossbar interconnect for low latency

Abstract

A system and method and computer program product for reducing the latency of signals communicated through a crossbar switch, the method including using at slave arbitration logic devices associated with Slave devices for which access is requested from one or more Master devices, two or more priority vector signals cycled among their use every clock cycle for selecting one of the requesting Master devices and updates the respective priority vector signal used every clock cycle. Similarly, each Master for which access is requested from one or more Slave devices, can have two or more priority vectors and can cycle among their use every clock cycle to further reduce latency and increase throughput performance via the crossbar.

Inventors:
;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1083210
Patent Number(s):
8370551
Application Number:
12/684,287
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
B554331
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Ohmacht, Martin, and Sugavanam, Krishnan. Arbitration in crossbar interconnect for low latency. United States: N. p., 2013. Web.
Ohmacht, Martin, & Sugavanam, Krishnan. Arbitration in crossbar interconnect for low latency. United States.
Ohmacht, Martin, and Sugavanam, Krishnan. Tue . "Arbitration in crossbar interconnect for low latency". United States. https://www.osti.gov/servlets/purl/1083210.
@article{osti_1083210,
title = {Arbitration in crossbar interconnect for low latency},
author = {Ohmacht, Martin and Sugavanam, Krishnan},
abstractNote = {A system and method and computer program product for reducing the latency of signals communicated through a crossbar switch, the method including using at slave arbitration logic devices associated with Slave devices for which access is requested from one or more Master devices, two or more priority vector signals cycled among their use every clock cycle for selecting one of the requesting Master devices and updates the respective priority vector signal used every clock cycle. Similarly, each Master for which access is requested from one or more Slave devices, can have two or more priority vectors and can cycle among their use every clock cycle to further reduce latency and increase throughput performance via the crossbar.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2013},
month = {2}
}

Works referenced in this record:

Hierarchical bus structure and memory access protocol for multiprocessor systems
patent, December 2008


Device control register for a processor block
patent, June 2010


Processor local bus bridge for an embedded processor block core in an integrated circuit
patent, August 2011


Arbiter having programmable arbitration points for undefined length burst accesses and method
patent-application, March 2005


Method of accessing memory via multiple slave ports
patent-application, December 2005


Data processing system with bus access retraction
patent-application, March 2006


Plural bus arbitrations per cycle via higher-frequency arbiter
patent-application, August 2006


Memory and Memory Communication System
patent-application, December 2007


Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure
patent-application, February 2011


    Works referencing / citing this record:

    Arbitration in crossbar interconnect for low latency
    patent, February 2013


    Arbitration in crossbar interconnect for low latency
    patent, February 2013


    Arbitration in crossbar interconnect for low latency
    patent, February 2013


    Arbitration in crossbar interconnect for low latency
    patent, February 2013


    Arbitration in crossbar interconnect for low latency
    patent, February 2013


    Arbitration in crossbar interconnect for low latency
    patent, February 2013


    Arbitration in crossbar interconnect for low latency
    patent, February 2013


    Arbitration in crossbar interconnect for low latency
    patent, February 2013