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Title: Simplifying and speeding the management of intra-node cache coherence

Abstract

A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.

Inventors:
 [1];  [2];  [3];  [4];  [5];  [6];  [7];  [3]
  1. Ridgefield, CT
  2. Croton on Hudson, NY
  3. Yorktown Heights, NY
  4. Mount Kisco, NY
  5. Irvington, NY
  6. Cortlandt Manor, NY
  7. Ossining, NY
Issue Date:
Research Org.:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1040782
Patent Number(s):
8161248
Application Number:
12/953,770
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
F - MECHANICAL ENGINEERING F04 - POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS F04D - NON-POSITIVE-DISPLACEMENT PUMPS
F - MECHANICAL ENGINEERING F24 - HEATING F24F - AIR-CONDITIONING
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Phillip, Hoenicke, Dirk, and Ohmacht, Martin. Simplifying and speeding the management of intra-node cache coherence. United States: N. p., 2012. Web.
Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Phillip, Hoenicke, Dirk, & Ohmacht, Martin. Simplifying and speeding the management of intra-node cache coherence. United States.
Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Phillip, Hoenicke, Dirk, and Ohmacht, Martin. Tue . "Simplifying and speeding the management of intra-node cache coherence". United States. https://www.osti.gov/servlets/purl/1040782.
@article{osti_1040782,
title = {Simplifying and speeding the management of intra-node cache coherence},
author = {Blumrich, Matthias A and Chen, Dong and Coteus, Paul W and Gara, Alan G and Giampapa, Mark E and Heidelberger, Phillip and Hoenicke, Dirk and Ohmacht, Martin},
abstractNote = {A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2012},
month = {4}
}