Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan
Abstract
An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.
- Inventors:
-
- Ridgefield, CT
- Rochester, MN
- Mount Kisco, NY
- Irvington, NY
- Cortlandt Manor, NY
- Leander, TX
- Yorktown Heights, NY
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1039559
- Patent Number(s):
- 8140925
- Application Number:
- 11/768,791
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- B554331
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2007 Jun 26
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 47 OTHER INSTRUMENTATION
Citation Formats
Bellofatto, Ralph E, Ellavsky, Matthew R, Gara, Alan G, Giampapa, Mark E, Gooding, Thomas M, Haring, Rudolf A, Hehenberger, Lance G, and Ohmacht, Martin. Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan. United States: N. p., 2012.
Web.
Bellofatto, Ralph E, Ellavsky, Matthew R, Gara, Alan G, Giampapa, Mark E, Gooding, Thomas M, Haring, Rudolf A, Hehenberger, Lance G, & Ohmacht, Martin. Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan. United States.
Bellofatto, Ralph E, Ellavsky, Matthew R, Gara, Alan G, Giampapa, Mark E, Gooding, Thomas M, Haring, Rudolf A, Hehenberger, Lance G, and Ohmacht, Martin. Tue .
"Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan". United States. https://www.osti.gov/servlets/purl/1039559.
@article{osti_1039559,
title = {Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan},
author = {Bellofatto, Ralph E and Ellavsky, Matthew R and Gara, Alan G and Giampapa, Mark E and Gooding, Thomas M and Haring, Rudolf A and Hehenberger, Lance G and Ohmacht, Martin},
abstractNote = {An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2012},
month = {3}
}
Save to My Library
You must Sign In or Create an Account in order to save documents to your library.
Works referenced in this record:
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
journal, August 2005
- Pande, P. P.; Grecu, C.; Jones, M.
- IEEE Transactions on Computers, Vol. 54, Issue 8
Performance evaluation of adaptive MPI
conference, January 2006
- Huang, Chao; Zheng, Gengbin; Kalé, Laxmikant
- Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06
Directory-based cache coherence in large-scale multiprocessors
journal, June 1990
- Chaiken, D.; Fields, C.; Kurihara, K.
- Computer, Vol. 23, Issue 6
Synchronization, coherence, and event ordering in multiprocessors
journal, February 1988
- Dubois, M.; Scheurich, C.; Briggs, F. A.
- Computer, Vol. 21, Issue 2
Overview of the Blue Gene/L system architecture
journal, March 2005
- Gara, A.; Blumrich, M. A.; Chen, D.
- IBM Journal of Research and Development, Vol. 49, Issue 2.3
Optimization of MPI collective communication on BlueGene/L systems
conference, January 2005
- Almási, George; Heidelberger, Philip; Archer, Charles J.
- Proceedings of the 19th annual international conference on Supercomputing - ICS '05
Intel 870: a building block for cost-effective, scalable servers
journal, March 2002
- Briggs, F.; Cekleov, M.; Creta, K.
- IEEE Micro, Vol. 22, Issue 2
Blue Gene/L advanced diagnostics environment
journal, March 2005
- Giampapa, M. E.; Bellofatto, R.; Blumrich, M. A.
- IBM Journal of Research and Development, Vol. 49, Issue 2.3