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Title: Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration

Abstract

In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.

Inventors:
 [1];  [2];  [3]
  1. Sandy, UT
  2. Rochester, NY
  3. Ithaca, NY
Issue Date:
Research Org.:
Univ. of Rochester, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1034620
Patent Number(s):
8103856
Application Number:
12/352,493
Assignee:
University of Rochester (Rochester, NY)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
DOE Contract Number:  
University of Rochester (Rochester, NY)
Resource Type:
Patent
Resource Relation:
Patent File Date: 2009 Jan 12
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Balasubramonian, Rajeev, Dwarkadas, Sandhya, and Albonesi, David. Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration. United States: N. p., 2012. Web.
Balasubramonian, Rajeev, Dwarkadas, Sandhya, & Albonesi, David. Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration. United States.
Balasubramonian, Rajeev, Dwarkadas, Sandhya, and Albonesi, David. Tue . "Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration". United States. https://www.osti.gov/servlets/purl/1034620.
@article{osti_1034620,
title = {Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration},
author = {Balasubramonian, Rajeev and Dwarkadas, Sandhya and Albonesi, David},
abstractNote = {In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Jan 24 00:00:00 EST 2012},
month = {Tue Jan 24 00:00:00 EST 2012}
}

Works referenced in this record:

The multiflow trace scheduling compiler
journal, May 1993


Dynamic Code Partitioning for Clustered Architectures
journal, February 2001


MediaBench: a tool for evaluating and synthesizing multimedia and communications systems
conference, December 1997


Multiscalar processors
conference, January 1995

  • Sohi, Gurindar S.; Breach, Scott E.; Vijaykumar, T. N.
  • Proceedings of the 22nd annual international symposium on Computer architecture - ISCA '95
  • https://doi.org/10.1145/223982.224451

Decoupling local variable accesses in a wide-issue superscalar processor
journal, May 1999


The Alpha 21264 microprocessor
journal, January 1999


Clock rate versus IPC: the end of the road for conventional microarchitectures
journal, May 2000


The SimpleScalar tool set, version 2.0
journal, June 1997


Focusing processor policies via critical-path prediction
conference, January 2001


Speculation techniques for improving load related instruction scheduling
journal, May 1999


Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
conference, January 2000

  • Balasubramonian, Rajeev; Albonesi, David; Buyuktosunoglu, Alper
  • Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture - MICRO 33
  • https://doi.org/10.1145/360128.360153

Efficient interconnects for clustered microarchitectures
conference, January 2002

  • Parcerisa, J. -M.; Sahuquillo, J.; Gonzalez, A.
  • 2002 International Conference on Parallel Architectures and Compilation Techniques. PACT 2002, Proceedings.International Conference on Parallel Architectures and Compilation Techniques
  • https://doi.org/10.1109/PACT.2002.1106028

Inherently lower-power high-performance superscalar architectures
journal, March 2001


An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches
conference, January 2001

  • Yang, S.; Powell, M. D.; Falsafi, B.
  • HPCA-7 - 7th IEEE Symposium on High Performance Computer Architecture, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture
  • https://doi.org/10.1109/HPCA.2001.903259

An Adaptive Issue Queue for Reduced Power at High Performance
book, January 2001


An empirical study of decentralized ILP execution models
journal, November 1998


An empirical study of the scalability aspects of instruction distribution algorithms for clustered processors
conference, January 2001


Processor coupling: integrating compile time and runtime scheduling for parallelism
conference, January 1992


Dynamically managing the communication-parallelism trade-off in future clustered processors
conference, January 2003

  • Balasubramonian, Rajeev; Dwarkadas, Sandhya; Albonesi, David H.
  • Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03
  • https://doi.org/10.1145/859618.859650

Partitioned register files for VLIWs: a preliminary analysis of tradeoffs
journal, December 1992


Simultaneous multithreading: maximizing on-chip parallelism
journal, May 1995


Dynamic cluster assignment mechanisms
conference, January 1999

  • Canal, R.; Parcerisa, J. M.; Gonzalez, A.
  • HPCA: 6th International Symposium on High-Performance Computer Architecutre, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)
  • https://doi.org/10.1109/HPCA.2000.824345

A framework for dynamic energy efficiency and temperature management
conference, January 2000


Power and energy reduction via pipeline balancing
conference, January 2001


A design space evaluation of grid processor architectures
conference, January 2001


Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources
conference, January 2001


A dynamic multithreading processor
conference, January 1998


Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors
conference, January 2000


Will physical scalability sabotage performance gains?
journal, January 1997


Dynamic prediction of critical path instructions
conference, January 2001


Dynamic IPC/clock rate optimization
journal, June 1998


Managing multi-configuration hardware via dynamic working set analysis
journal, May 2002


The multicluster architecture: reducing cycle time through partitioning
conference, January 1997


Positional adaptation of processors: application to energy reduction
conference, January 2003


Complexity-effective superscalar processors
conference, January 1997


Access region locality for high-bandwidth processor memory system design
conference, November 1999