Message passing with a limited number of DMA byte counters

Blocksome, Michael; Chen, Dong; Giampapa, Mark E; Heidelberger, Philip; Kumar, Sameer; Parker, Jeffrey J

Title: Message passing with a limited number of DMA byte counters

Abstract

A method for passing messages in a parallel computer system constructed as a plurality of compute nodes interconnected as a network where each compute node includes a DMA engine but includes only a limited number of byte counters for tracking a number of bytes that are sent or received by the DMA engine, where the byte counters may be used in shared counter or exclusive counter modes of operation. The method includes using rendezvous protocol, a source compute node deterministically sending a request to send (RTS) message with a single RTS descriptor using an exclusive injection counter to track both the RTS message and message data to be sent in association with the RTS message, to a destination compute node such that the RTS descriptor indicates to the destination compute node that the message data will be adaptively routed to the destination node. Using one DMA FIFO at the source compute node, the RTS descriptors are maintained for rendezvous messages destined for the destination compute node to ensure proper message data ordering thereat. Using a reception counter at a DMA engine, the destination compute node tracks reception of the RTS and associated message data and sends a clear to sendmore » « less

Inventors:

Blocksome, Michael ^[1]; Chen, Dong ^[2]; Giampapa, Mark E ^[3]; Heidelberger, Philip ^[4]; Kumar, Sameer ^[5]; Parker, Jeffrey J ^[1]

Rochester, MN
Croton on Hudson, NY
Irvington, NY
Cortlandt Manor, NY
White Plains, NY

Issue Date:: 2011-10-04

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1029268

Patent Number(s):: 8032892

Application Number:: 11/768,813

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F15/17356 - {Indirect interconnection networks}
G06F9/546 - {Message passing systems or structures, e.g. queues}

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DOE Contract Number:: B554331

Resource Type:: Patent

Resource Relation:: Patent File Date: 2007 Jun 26

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Blocksome, Michael, Chen, Dong, Giampapa, Mark E, Heidelberger, Philip, Kumar, Sameer, and Parker, Jeffrey J. Message passing with a limited number of DMA byte counters.  United States: N. p., 2011. 
        Web.

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                    Blocksome, Michael, Chen, Dong, Giampapa, Mark E, Heidelberger, Philip, Kumar, Sameer, & Parker, Jeffrey J. Message passing with a limited number of DMA byte counters.  United States.

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                    Blocksome, Michael, Chen, Dong, Giampapa, Mark E, Heidelberger, Philip, Kumar, Sameer, and Parker, Jeffrey J. Tue .  
        "Message passing with a limited number of DMA byte counters".  United States.  https://www.osti.gov/servlets/purl/1029268.

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@article{osti_1029268,

  title        = {Message passing with a limited number of DMA byte counters},

  author       = {Blocksome, Michael and Chen, Dong and Giampapa, Mark E and Heidelberger, Philip and Kumar, Sameer and Parker, Jeffrey J},

  abstractNote = {A method for passing messages in a parallel computer system constructed as a plurality of compute nodes interconnected as a network where each compute node includes a DMA engine but includes only a limited number of byte counters for tracking a number of bytes that are sent or received by the DMA engine, where the byte counters may be used in shared counter or exclusive counter modes of operation. The method includes using rendezvous protocol, a source compute node deterministically sending a request to send (RTS) message with a single RTS descriptor using an exclusive injection counter to track both the RTS message and message data to be sent in association with the RTS message, to a destination compute node such that the RTS descriptor indicates to the destination compute node that the message data will be adaptively routed to the destination node. Using one DMA FIFO at the source compute node, the RTS descriptors are maintained for rendezvous messages destined for the destination compute node to ensure proper message data ordering thereat. Using a reception counter at a DMA engine, the destination compute node tracks reception of the RTS and associated message data and sends a clear to send (CTS) message to the source node in a rendezvous protocol form of a remote get to accept the RTS message and message data and processing the remote get (CTS) by the source compute node DMA engine to provide the message data to be sent.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2011},

  month        = {10}

}

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Works referenced in this record:

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
journal, August 2005

Pande, P. P.; Grecu, C.; Jones, M.
IEEE Transactions on Computers, Vol. 54, Issue 8
https://doi.org/10.1109/TC.2005.134

Performance evaluation of adaptive MPI
conference, January 2006

Huang, Chao; Zheng, Gengbin; Kalé, Laxmikant
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06
https://doi.org/10.1145/1122971.1122976

Directory-based cache coherence in large-scale multiprocessors
journal, June 1990

Chaiken, D.; Fields, C.; Kurihara, K.
Computer, Vol. 23, Issue 6
https://doi.org/10.1109/2.55500

Synchronization, coherence, and event ordering in multiprocessors
journal, February 1988

Dubois, M.; Scheurich, C.; Briggs, F. A.
Computer, Vol. 21, Issue 2
https://doi.org/10.1109/2.15

Overview of the Blue Gene/L system architecture
journal, March 2005

Gara, A.; Blumrich, M. A.; Chen, D.
IBM Journal of Research and Development, Vol. 49, Issue 2.3
https://doi.org/10.1147/rd.492.0195

Optimization of MPI collective communication on BlueGene/L systems
conference, January 2005

Almási, George; Heidelberger, Philip; Archer, Charles J.
Proceedings of the 19th annual international conference on Supercomputing - ICS '05
https://doi.org/10.1145/1088149.1088183

Intel 870: a building block for cost-effective, scalable servers
journal, March 2002

Briggs, F.; Cekleov, M.; Creta, K.
IEEE Micro, Vol. 22, Issue 2
https://doi.org/10.1109/MM.2002.997878

Blue Gene/L advanced diagnostics environment
journal, March 2005

Giampapa, M. E.; Bellofatto, R.; Blumrich, M. A.
IBM Journal of Research and Development, Vol. 49, Issue 2.3
https://doi.org/10.1147/rd.492.0319

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Title: Message passing with a limited number of DMA byte counters

Abstract

Citation Formats

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures journal, August 2005

Performance evaluation of adaptive MPI conference, January 2006

Directory-based cache coherence in large-scale multiprocessors journal, June 1990

Synchronization, coherence, and event ordering in multiprocessors journal, February 1988

Overview of the Blue Gene/L system architecture journal, March 2005

Optimization of MPI collective communication on BlueGene/L systems conference, January 2005

Intel 870: a building block for cost-effective, scalable servers journal, March 2002

Blue Gene/L advanced diagnostics environment journal, March 2005

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
journal, August 2005

Performance evaluation of adaptive MPI
conference, January 2006

Directory-based cache coherence in large-scale multiprocessors
journal, June 1990

Synchronization, coherence, and event ordering in multiprocessors
journal, February 1988

Overview of the Blue Gene/L system architecture
journal, March 2005

Optimization of MPI collective communication on BlueGene/L systems
conference, January 2005

Intel 870: a building block for cost-effective, scalable servers
journal, March 2002

Blue Gene/L advanced diagnostics environment
journal, March 2005