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Title: Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations

Abstract

Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the execution unit. The execution unit has logic that implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA). The floating point vector registers of the vector register file store both scalar and floating point values as vectors having a plurality of vector elements. The processor may be part of a data processing system.

Inventors:
 [1]
  1. Chappaqua, NY
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1018063
Patent Number(s):
7900025
Application Number:
12/250,575
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 2008 Oct 14
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Gschwind, Michael K. Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations. United States: N. p., 2011. Web.
Gschwind, Michael K. Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations. United States.
Gschwind, Michael K. Tue . "Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations". United States. https://www.osti.gov/servlets/purl/1018063.
@article{osti_1018063,
title = {Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations},
author = {Gschwind, Michael K},
abstractNote = {Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the execution unit. The execution unit has logic that implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA). The floating point vector registers of the vector register file store both scalar and floating point values as vectors having a plurality of vector elements. The processor may be part of a data processing system.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2011},
month = {3}
}

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Works referenced in this record:

Optimizing Compiler for the CELL Processor
conference, January 2005

  • Eichenberger, A. E.; O'Brien, K.; O'Brien, K.
  • PACT 2005. 14th International Conference on Parallel Architectures and Compilation Techniques, 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)
  • https://doi.org/10.1109/PACT.2005.33

IBM PowerPC 440 FPU with complex-arithmetic extensions
journal, March 2005


Synergistic Processing in Cell's Multicore Architecture
journal, March 2006


Vectorization for SIMD architectures with alignment constraints
conference, January 2004

  • Eichenberger, Alexandre E.; Wu, Peng; O'Brien, Kevin
  • Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation - PLDI '04
  • https://doi.org/10.1145/996841.996853

Using advanced compiler technology to exploit the performance of the Cell Broadband Engine™ architecture
journal, January 2006


An integrated simdization framework using virtual vectors
conference, January 2005


DFG Program
journal, December 1999