skip to main content
DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: System and method for programmable bank selection for banked memory subsystems

Abstract

A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

Inventors:
 [1];  [2];  [3];  [4];  [5];  [6];  [7];  [8]
  1. Ridgefield, CT
  2. Croton on Hudson, NY
  3. Mount Kisco, NY
  4. Irvington, NY
  5. Seebruck-Seeon, DE
  6. Yorktown Heights, NY
  7. Chappaqua, NY
  8. Mahopac, NY
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1017170
Patent Number(s):
7793038
Application Number:
11/768,805
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
DOE Contract Number:  
B554331
Resource Type:
Patent
Country of Publication:
United States
Language:
English

Citation Formats

Blumrich, Matthias A, Chen, Dong, Gara, Alan G, Giampapa, Mark E, Hoenicke, Dirk, Ohmacht, Martin, Salapura, Valentina, and Sugavanam, Krishnan. System and method for programmable bank selection for banked memory subsystems. United States: N. p., 2010. Web.
Blumrich, Matthias A, Chen, Dong, Gara, Alan G, Giampapa, Mark E, Hoenicke, Dirk, Ohmacht, Martin, Salapura, Valentina, & Sugavanam, Krishnan. System and method for programmable bank selection for banked memory subsystems. United States.
Blumrich, Matthias A, Chen, Dong, Gara, Alan G, Giampapa, Mark E, Hoenicke, Dirk, Ohmacht, Martin, Salapura, Valentina, and Sugavanam, Krishnan. Tue . "System and method for programmable bank selection for banked memory subsystems". United States. https://www.osti.gov/servlets/purl/1017170.
@article{osti_1017170,
title = {System and method for programmable bank selection for banked memory subsystems},
author = {Blumrich, Matthias A and Chen, Dong and Gara, Alan G and Giampapa, Mark E and Hoenicke, Dirk and Ohmacht, Martin and Salapura, Valentina and Sugavanam, Krishnan},
abstractNote = {A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2010},
month = {9}
}

Patent:

Save / Share:

Works referenced in this record:

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
journal, August 2005


Performance evaluation of adaptive MPI
conference, January 2006

  • Huang, Chao; Zheng, Gengbin; Kalé, Laxmikant
  • Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06
  • https://doi.org/10.1145/1122971.1122976

Directory-based cache coherence in large-scale multiprocessors
journal, June 1990


Synchronization, coherence, and event ordering in multiprocessors
journal, February 1988


Overview of the Blue Gene/L system architecture
journal, March 2005


Optimization of MPI collective communication on BlueGene/L systems
conference, January 2005


Intel 870: a building block for cost-effective, scalable servers
journal, March 2002


Blue Gene/L advanced diagnostics environment
journal, March 2005