Computer hardware fault administration

Archer, Charles J; Megerian, Mark G; Ratterman, Joseph D; Smith, Brian E

Title: Computer hardware fault administration

Abstract

Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

Inventors:

Archer, Charles J ^[1]; Megerian, Mark G ^[1]; Ratterman, Joseph D ^[1]; Smith, Brian E ^[1]

Rochester, MN

Issue Date:: 2010-09-14

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1017167

Patent Number(s):: 7796527

Application Number:: 11/279,579

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/2007 - {using redundant communication media}
G06F11/2005 - {using redundant communication controllers}
G06F11/2012 - {and using different communication protocols}

Show less

DOE Contract Number:: B519700

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Citation Formats


                    Archer, Charles J, Megerian, Mark G, Ratterman, Joseph D, and Smith, Brian E. Computer hardware fault administration.  United States: N. p., 2010. 
        Web.

Copy to clipboard


                    Archer, Charles J, Megerian, Mark G, Ratterman, Joseph D, & Smith, Brian E. Computer hardware fault administration.  United States.

Copy to clipboard


                    Archer, Charles J, Megerian, Mark G, Ratterman, Joseph D, and Smith, Brian E. Tue .  
        "Computer hardware fault administration".  United States.  https://www.osti.gov/servlets/purl/1017167.

Copy to clipboard


                    
@article{osti_1017167,

  title        = {Computer hardware fault administration},

  author       = {Archer, Charles J and Megerian, Mark G and Ratterman, Joseph D and Smith, Brian E},

  abstractNote = {Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2010},

  month        = {9}

}

Copy to clipboard

Patent:

Save / Share:

Export Metadata

Save to My Library

Works referenced in this record:

An Overview of the BlueGene/L Supercomputer
conference, January 2002

Adiga, N. R.; Almasi, G.; Almasi, G. S.
ACM/IEEE SC 2002 Conference (SC'02)
https://doi.org/10.1109/SC.2002.10017

Similar Records in DOE Patents and OSTI.GOV collections:

Locating hardware faults in a data communications network of a parallel computer

Patent Archer, Charles J [Rochester, MN]; Megerian, Mark G [Rochester, MN]; Ratterman, Joseph D [Rochester, MN]; ...

Hardware faults location in a data communications network of a parallel computer. Such a parallel computer includes a plurality of compute nodes and a data communications network that couples the compute nodes for data communications and organizes the compute node as a tree. Locating hardware faults includes identifying a next compute node as a parent node and a root of a parent test tree, identifying for each child compute node of the parent node a child test tree having the child compute node as root, running a same test suite on the parent test tree and each child test tree,more » « less
Full Text Available
Solver for hardware based computing

Patent Nwankpa, Chika; Deese, Anthony; St. Leger, Aaron; ...

Full-AC load flow constitutes a core computation in power system analysis. A performance gain with a hardware implementation of a sparse-linear solver using a Field Programmable Gate Array (FPGA) is achieved by use of a DC network emulation of the power system bus. Analog Behavioral Models (ABMs) are used in an efficient strategy for designing analog emulation engines for large-scale power system computation. A generator model is also developed using analog circuits for load flow emulation for power system analysis to reduce computation time. The generator model includes reconfigurable parameters using operational transconductance amplifiers (OTAs). The circuit module is usedmore » « less
Full Text Available
Hardware packet pacing using a DMA in a parallel computer

Patent Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.
Full Text Available
Majorana pair based qubits for fault tolerant quantum computing architecture using superconducting gold surface states

Patent Moodera, Jagadeesh S.; Lee, Patrick A.; Wei, Peng; ...

Under certain conditions, a fermion in a superconductor can separate in space into two parts known as Majorana zero modes, which are immune to decoherence from local noise sources and are attractive building blocks for quantum computers. Here we disclose a metal-based heterostructure platform to produce these Majorana zero modes which utilizes the surface states of certain metals in combination with a ferromagnetic insulator and a superconductor. This platform has the advantage of having a robust energy scale and the possibility of realizing complex circuit designs using lithographic methods. The Majorana zero modes are interrogated using planar tunnel junctions andmore » « less
Full Text Available
Methods and apparatus using commutative error detection values for fault isolation in multiple node computers

Patent Almasi, Gheorghe [Ardsley, NY]; Blumrich, Matthias Augustin [Ridgefield, CT]; Chen, Dong [Croton-On-Hudson, NY]; ...

Methods and apparatus perform fault isolation in multiple node computing systems using commutative error detection values for--example, checksums--to identify and to isolate faulty nodes. When information associated with a reproducible portion of a computer program is injected into a network by a node, a commutative error detection value is calculated. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values associated with the node and stores them in memory. When the computer program is executed again by the multiple node computer system, new commutative error detection values are created and stored inmore » « less
Full Text Available

Similar Records

Title: Computer hardware fault administration

Abstract

Citation Formats

An Overview of the BlueGene/L Supercomputer conference, January 2002

An Overview of the BlueGene/L Supercomputer
conference, January 2002