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Title: DMA engine for repeating communication patterns

Abstract

A parallel computer system is constructed as a network of interconnected compute nodes to operate a global message-passing application for performing communications across the network. Each of the compute nodes includes one or more individual processors with memories which run local instances of the global message-passing application operating at each compute node to carry out local processing operations independent of processing operations carried out at other compute nodes. Each compute node also includes a DMA engine constructed to interact with the application via Injection FIFO Metadata describing multiple Injection FIFOs where each Injection FIFO may containing an arbitrary number of message descriptors in order to process messages with a fixed processing overhead irrespective of the number of message descriptors included in the Injection FIFO.

Inventors:
 [1];  [2];  [3];  [4];  [5];  [6]
  1. (Croton on Hudson, NY)
  2. (Mount Kisco, NY)
  3. (Irvington, NY)
  4. (Cortlandt Manor, NY)
  5. (Esslingen, DE)
  6. (Danville, CA)
Issue Date:
Research Org.:
International Business Machines Corporation (Armonk, NY)
Sponsoring Org.:
USDOE
OSTI Identifier:
1017165
Patent Number(s):
7,802,025
Application Number:
11/768,795
Assignee:
International Business Machines Corporation (Armonk, NY) OSTI
DOE Contract Number:  
B554331
Resource Type:
Patent
Country of Publication:
United States
Language:
English

Citation Formats

Chen, Dong, Gara, Alan G., Giampapa, Mark E., Heidelberger, Philip, Steinmacher-Burow, Burkhard, and Vranas, Pavlos. DMA engine for repeating communication patterns. United States: N. p., 2010. Web.
Chen, Dong, Gara, Alan G., Giampapa, Mark E., Heidelberger, Philip, Steinmacher-Burow, Burkhard, & Vranas, Pavlos. DMA engine for repeating communication patterns. United States.
Chen, Dong, Gara, Alan G., Giampapa, Mark E., Heidelberger, Philip, Steinmacher-Burow, Burkhard, and Vranas, Pavlos. Tue . "DMA engine for repeating communication patterns". United States. https://www.osti.gov/servlets/purl/1017165.
@article{osti_1017165,
title = {DMA engine for repeating communication patterns},
author = {Chen, Dong and Gara, Alan G. and Giampapa, Mark E. and Heidelberger, Philip and Steinmacher-Burow, Burkhard and Vranas, Pavlos},
abstractNote = {A parallel computer system is constructed as a network of interconnected compute nodes to operate a global message-passing application for performing communications across the network. Each of the compute nodes includes one or more individual processors with memories which run local instances of the global message-passing application operating at each compute node to carry out local processing operations independent of processing operations carried out at other compute nodes. Each compute node also includes a DMA engine constructed to interact with the application via Injection FIFO Metadata describing multiple Injection FIFOs where each Injection FIFO may containing an arbitrary number of message descriptors in order to process messages with a fixed processing overhead irrespective of the number of message descriptors included in the Injection FIFO.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2010},
month = {9}
}

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