Space and power efficient hybrid counters array
Abstract
A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.
- Inventors:
-
- Mount Kisco, NY
- Chappaqua, NY
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1015352
- Patent Number(s):
- 7688931
- Application Number:
- 12/120,416
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
- DOE Contract Number:
- B542702
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Gara, Alan G, and Salapura, Valentina. Space and power efficient hybrid counters array. United States: N. p., 2010.
Web.
Gara, Alan G, & Salapura, Valentina. Space and power efficient hybrid counters array. United States.
Gara, Alan G, and Salapura, Valentina. Tue .
"Space and power efficient hybrid counters array". United States. https://www.osti.gov/servlets/purl/1015352.
@article{osti_1015352,
title = {Space and power efficient hybrid counters array},
author = {Gara, Alan G and Salapura, Valentina},
abstractNote = {A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Mar 30 00:00:00 EDT 2010},
month = {Tue Mar 30 00:00:00 EDT 2010}
}
Works referenced in this record:
Maintaining statistics counters in router line cards
journal, January 2002
- Shah, D.; Iyer, S.; Prahhakar, B.
- IEEE Micro, Vol. 22, Issue 1