Static power reduction for midpoint-terminated busses
Abstract
A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well.
- Inventors:
-
- Yorktown Heights, NY
- Brewster, NY
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1013026
- Patent Number(s):
- 7873843
- Application Number:
- 11/768,552
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
- DOE Contract Number:
- B 554331
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Coteus, Paul W, and Takken, Todd. Static power reduction for midpoint-terminated busses. United States: N. p., 2011.
Web.
Coteus, Paul W, & Takken, Todd. Static power reduction for midpoint-terminated busses. United States.
Coteus, Paul W, and Takken, Todd. Tue .
"Static power reduction for midpoint-terminated busses". United States. https://www.osti.gov/servlets/purl/1013026.
@article{osti_1013026,
title = {Static power reduction for midpoint-terminated busses},
author = {Coteus, Paul W and Takken, Todd},
abstractNote = {A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2011},
month = {1}
}
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