---
code_id: 166589
site_ownership_code: "LBNL"
open_source: true
repository_link: "https://socks.lbl.gov/mvega/chisel-fp-generators"
project_type: "OS"
software_type: "S"
official_use_only: {}
developers:
- email: "JShalf@lbl.gov"
  orcid: ""
  first_name: "John"
  last_name: "Shalf"
  middle_name: "M."
  affiliations:
  - "Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)"
- email: "dtpopovici@lbl.gov"
  orcid: ""
  first_name: "Doru Adrian Thom"
  last_name: "Popovici"
  middle_name: ""
  affiliations:
  - "Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)"
- email: "MVega@lbl.gov"
  orcid: ""
  first_name: "Mario"
  last_name: "Vega"
  middle_name: ""
  affiliations:
  - "Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)"
- email: "XiaokunYang@lbl.gov"
  orcid: ""
  first_name: "Xiaokun"
  last_name: "Yang"
  middle_name: ""
  affiliations:
  - "Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)"
  - "University of Houston - Clear Lake"
contributors: []
sponsoring_organizations:
- organization_name: "USDOE"
  funding_identifiers:
  - identifier_type: "AwardNumber"
    identifier_value: "National Science Foundation (NSF) No. 2243980"
  - identifier_type: "AwardNumber"
    identifier_value: "DOD NATIONAL SECURITY AGENCY (NSA) No. AWD7452 (EAOC0185067)"
  primary_award: "AC02-05CH11231"
  DOE: true
contributing_organizations: []
research_organizations:
- organization_name: "Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United\
    \ States)"
  DOE: true
- organization_name: "University of Houston - Clear Lake"
  DOE: true
related_identifiers: []
award_dois: []
release_date: "2025-02-04"
software_title: "Code Generators for Floating-Point Unit Design in Integrated Circuits\
  \ (OpenFloat) v1.0"
acronym: "OpenFloat v1.0"
doi: "https://doi.org/10.11578/dc.20251009.3"
description: "This IP provides a comprehensive set of code generators for various\
  \ floating-point units (FPUs) essential for integrated circuit design and integration,\
  \ targeting a broad spectrum of applications, including machine learning and scientific\
  \ computing. The suite includes FP adders, multipliers, subtractors, dividers, reciprocals,\
  \ exponentials, square roots, trigonometric functions (sine, cosine, arctangent),\
  \ and more. It supports customizable hardware design parameters, such as precision\
  \ (16, 32, 64, and 128 bits) and pipeline depths, offering users enhanced flexibility\
  \ and productivity. The generated code is in an industry-standard hardware description\
  \ language, ensuring compatibility with standard design flows, including simulation,\
  \ verification, synthesis, and implementation on both field-programmable gate arrays\
  \ (FPGAs) and application-specific integrated circuits (ASICs)."
programming_languages: []
country_of_origin: "United States"
project_keywords: []
licenses:
- "BSD 3-clause \"New\" or \"Revised\" License"
recipient_org: "LBNL"
site_accession_number: "2025-018"
date_record_added: "2025-10-09"
date_record_updated: "2025-10-09"
is_file_certified: false
last_editor: "ntheodore@lbl.gov"
is_limited: false
links:
- rel: "citation"
  href: "https://www.osti.gov/doecode/biblio/166589"