166589 LBNL true https://socks.lbl.gov/mvega/chisel-fp-generators OS S 2025-02-04 Code Generators for Floating-Point Unit Design in Integrated Circuits (OpenFloat) v1.0 OpenFloat v1.0 https://doi.org/10.11578/dc.20251009.3 This IP provides a comprehensive set of code generators for various floating-point units (FPUs) essential for integrated circuit design and integration, targeting a broad spectrum of applications, including machine learning and scientific computing. The suite includes FP adders, multipliers, subtractors, dividers, reciprocals, exponentials, square roots, trigonometric functions (sine, cosine, arctangent), and more. It supports customizable hardware design parameters, such as precision (16, 32, 64, and 128 bits) and pipeline depths, offering users enhanced flexibility and productivity. The generated code is in an industry-standard hardware description language, ensuring compatibility with standard design flows, including simulation, verification, synthesis, and implementation on both field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). United States LBNL 2025-018 2025-10-09 2025-10-09 false ntheodore@lbl.gov false JShalf@lbl.gov John Shalf M. Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States) dtpopovici@lbl.gov Doru Adrian Thom Popovici Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States) MVega@lbl.gov Mario Vega Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States) XiaokunYang@lbl.gov Xiaokun Yang Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States) University of Houston - Clear Lake USDOE AC02-05CH11231 true AwardNumber National Science Foundation (NSF) No. 2243980 AwardNumber DOD NATIONAL SECURITY AGENCY (NSA) No. AWD7452 (EAOC0185067) Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States) true University of Houston - Clear Lake true BSD 3-clause "New" or "Revised" License