Abstract
ZFP is a floating-point compression format gaining traction in high-performance computing applications. A
software implementation has demonstrated the ability to reduce data movement across communication
channels and to reduce the footprint of floating-point arrays in memory. Nevertheless, any benefit in
performance is limited to the spare compute cycles available before reaching bandwidth limitations. A
hardware implementation of ZFP has the potential to substantially improve HPC application performance.
Hardware compression speedup over software alone on a single CPU core ranges from 15x for 1-D
arrays to over 200x for 3-D arrays.
The implementation of ZFP is sourced in SystemC to facilitate its evaluation in various architectures. The
encode pipeline consists of several modules. Uncompressed blocks of floating-point numbers in IEEE
format flow into the pipeline in a stream and a compressed bitstream flows out from the pipeline. The
decode pipeline is the inverse of the encode pipeline. A modular design enables formats other than IEEE
(such as posits) to be considered with minor adaptations. Best performance will be realized from the
hardware ZFP unit when batches of blocks are processed at a time. The implementation supports 1-D, 2-
D and 3-D blocks of floating-point numbers.
The hardware implementation of ZFP has been validated with the software implementation of ZFP. C++
template parameters are used to specify
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- Developers:
-
Lloyd, G [1] ; Lindstrom, Peter
- Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
- Release Date:
- 2019-09-17
- Project Type:
- Open Source, Publicly Available Repository
- Software Type:
- Scientific
- Version:
- 0.5
- Licenses:
-
BSD 3-clause "New" or "Revised" License
- Sponsoring Org.:
-
USDOE National Nuclear Security Administration (NNSA)Primary Award/Contract Number:AC52-07NA27344
- Code ID:
- 40147
- Site Accession Number:
- LLNL-CODE-811758
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Country of Origin:
- United States
Citation Formats
Lloyd, G S., and Lindstrom, Peter G.
ZFP Hardware Implementation.
Computer Software.
https://github.com/LLNL/zhw.git.
USDOE National Nuclear Security Administration (NNSA).
17 Sep. 2019.
Web.
doi:10.11578/dc.20200727.3.
Lloyd, G S., & Lindstrom, Peter G.
(2019, September 17).
ZFP Hardware Implementation.
[Computer software].
https://github.com/LLNL/zhw.git.
https://doi.org/10.11578/dc.20200727.3.
Lloyd, G S., and Lindstrom, Peter G.
"ZFP Hardware Implementation." Computer software.
September 17, 2019.
https://github.com/LLNL/zhw.git.
https://doi.org/10.11578/dc.20200727.3.
@misc{
doecode_40147,
title = {ZFP Hardware Implementation},
author = {Lloyd, G S. and Lindstrom, Peter G.},
abstractNote = {ZFP is a floating-point compression format gaining traction in high-performance computing applications. A
software implementation has demonstrated the ability to reduce data movement across communication
channels and to reduce the footprint of floating-point arrays in memory. Nevertheless, any benefit in
performance is limited to the spare compute cycles available before reaching bandwidth limitations. A
hardware implementation of ZFP has the potential to substantially improve HPC application performance.
Hardware compression speedup over software alone on a single CPU core ranges from 15x for 1-D
arrays to over 200x for 3-D arrays.
The implementation of ZFP is sourced in SystemC to facilitate its evaluation in various architectures. The
encode pipeline consists of several modules. Uncompressed blocks of floating-point numbers in IEEE
format flow into the pipeline in a stream and a compressed bitstream flows out from the pipeline. The
decode pipeline is the inverse of the encode pipeline. A modular design enables formats other than IEEE
(such as posits) to be considered with minor adaptations. Best performance will be realized from the
hardware ZFP unit when batches of blocks are processed at a time. The implementation supports 1-D, 2-
D and 3-D blocks of floating-point numbers.
The hardware implementation of ZFP has been validated with the software implementation of ZFP. C++
template parameters are used to specify the bit width of floating-point numbers and the array dimension
of the encoder. A test bench program has been created with several test cases, some with continuous
data that is ideal for ZFP, and others with extreme cases containing numbers near or at the maximum or
minimum values supported by the number format.},
doi = {10.11578/dc.20200727.3},
url = {https://doi.org/10.11578/dc.20200727.3},
howpublished = {[Computer Software] \url{https://doi.org/10.11578/dc.20200727.3}},
year = {2019},
month = {sep}
}