Abstract
This IP provides a comprehensive set of code generators for various floating-point units (FPUs) essential for integrated circuit design and integration, targeting a broad spectrum of applications, including machine learning and scientific computing. The suite includes FP adders, multipliers, subtractors, dividers, reciprocals, exponentials, square roots, trigonometric functions (sine, cosine, arctangent), and more. It supports customizable hardware design parameters, such as precision (16, 32, 64, and 128 bits) and pipeline depths, offering users enhanced flexibility and productivity. The generated code is in an industry-standard hardware description language, ensuring compatibility with standard design flows, including simulation, verification, synthesis, and implementation on both field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).
- Developers:
-
Shalf, John [1] ; Popovici, Doru Adrian Thom [1] ; Vega, Mario [1] ; Yang, Xiaokun [1][2]
- Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
- University of Houston - Clear Lake
- Release Date:
- 2025-02-04
- Project Type:
- Open Source, Publicly Available Repository
- Software Type:
- Scientific
- Licenses:
-
BSD 3-clause "New" or "Revised" License
- Sponsoring Org.:
-
USDOEPrimary Award/Contract Number:AC02-05CH11231Other Award/Contract Number:National Science Foundation (NSF) No. 2243980DOD NATIONAL SECURITY AGENCY (NSA) No. AWD7452 (EAOC0185067)
- Code ID:
- 166589
- Site Accession Number:
- 2025-018
- Research Org.:
- Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)University of Houston - Clear Lake
- Country of Origin:
- United States
Citation Formats
Shalf, John M., Popovici, Doru Adrian Thom, Vega, Mario, and Yang, Xiaokun.
Code Generators for Floating-Point Unit Design in Integrated Circuits (OpenFloat) v1.0.
Computer Software.
https://socks.lbl.gov/mvega/chisel-fp-generators.
USDOE.
04 Feb. 2025.
Web.
doi:10.11578/dc.20251009.3.
Shalf, John M., Popovici, Doru Adrian Thom, Vega, Mario, & Yang, Xiaokun.
(2025, February 04).
Code Generators for Floating-Point Unit Design in Integrated Circuits (OpenFloat) v1.0.
[Computer software].
https://socks.lbl.gov/mvega/chisel-fp-generators.
https://doi.org/10.11578/dc.20251009.3.
Shalf, John M., Popovici, Doru Adrian Thom, Vega, Mario, and Yang, Xiaokun.
"Code Generators for Floating-Point Unit Design in Integrated Circuits (OpenFloat) v1.0." Computer software.
February 04, 2025.
https://socks.lbl.gov/mvega/chisel-fp-generators.
https://doi.org/10.11578/dc.20251009.3.
@misc{
doecode_166589,
title = {Code Generators for Floating-Point Unit Design in Integrated Circuits (OpenFloat) v1.0},
author = {Shalf, John M. and Popovici, Doru Adrian Thom and Vega, Mario and Yang, Xiaokun},
abstractNote = {This IP provides a comprehensive set of code generators for various floating-point units (FPUs) essential for integrated circuit design and integration, targeting a broad spectrum of applications, including machine learning and scientific computing. The suite includes FP adders, multipliers, subtractors, dividers, reciprocals, exponentials, square roots, trigonometric functions (sine, cosine, arctangent), and more. It supports customizable hardware design parameters, such as precision (16, 32, 64, and 128 bits) and pipeline depths, offering users enhanced flexibility and productivity. The generated code is in an industry-standard hardware description language, ensuring compatibility with standard design flows, including simulation, verification, synthesis, and implementation on both field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).},
doi = {10.11578/dc.20251009.3},
url = {https://doi.org/10.11578/dc.20251009.3},
howpublished = {[Computer Software] \url{https://doi.org/10.11578/dc.20251009.3}},
year = {2025},
month = {feb}
}