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Title: Method and system for an on-chip AC self-test controller

Abstract

A method and system for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation are provided. The method includes applying a long data capture pulse to a first test register in response to the system clock, applying an at speed data launch pulse to the first test register in response to the system clock, inputting the data from the first register to a logic path in response to applying the at speed data launch pulse to the first test register, applying an at speed data capture pulse to a second test register in response to the system clock, inputting the logic path output to the second test register in response to applying the at speed data capture pulse to the second test register, and applying a long data launch pulse to the second test register in response to the system clock.

Inventors:
 [1];  [2];  [3]
  1. Rhinebeck, NY
  2. Poughkeepsie, NY
  3. Fishkill, NY
Publication Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
984512
Patent Number(s):
7,430,698
Application Number:
11/323,449
Assignee:
International Business Machines Corporation (Armonk, NY)
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING

Citation Formats

Flanagan, John D, Herring, Jay R, and Lo, Tin-Chee. Method and system for an on-chip AC self-test controller. United States: N. p., 2008. Web.
Flanagan, John D, Herring, Jay R, & Lo, Tin-Chee. Method and system for an on-chip AC self-test controller. United States.
Flanagan, John D, Herring, Jay R, and Lo, Tin-Chee. Tue . "Method and system for an on-chip AC self-test controller". United States. https://www.osti.gov/servlets/purl/984512.
@article{osti_984512,
title = {Method and system for an on-chip AC self-test controller},
author = {Flanagan, John D and Herring, Jay R and Lo, Tin-Chee},
abstractNote = {A method and system for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation are provided. The method includes applying a long data capture pulse to a first test register in response to the system clock, applying an at speed data launch pulse to the first test register in response to the system clock, inputting the data from the first register to a logic path in response to applying the at speed data launch pulse to the first test register, applying an at speed data capture pulse to a second test register in response to the system clock, inputting the logic path output to the second test register in response to applying the at speed data capture pulse to the second test register, and applying a long data launch pulse to the second test register in response to the system clock.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2008},
month = {9}
}

Patent:

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