Several key issues on implementing delay line based TDCs using FPGAs
Journal Article
·
· Submitted to IEEE TRANS.NUCL.SCI.
OSTI ID:971382
Several topics in FPGA delay line based TDCs are discussed in this document. First, FPGA specific issues such as considerations on the delay line choice in different FPGA families, Wave Union Launchers, 'bubble proof' encoding logic, etc. are examined. Next, common problems for both FPGA TDCs and ASIC TDCs such as schemes of coarse time counter implementation, bin-by-bin calibration and noise issues due to single ended signals are discussed. Several resource/power saving design approaches for various processing stages are described in the document.
- Research Organization:
- Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC02-07CH11359
- OSTI ID:
- 971382
- Report Number(s):
- FERMILAB-PUB-09-608-E; TRN: US1001178
- Journal Information:
- Submitted to IEEE TRANS.NUCL.SCI., Journal Name: Submitted to IEEE TRANS.NUCL.SCI.
- Country of Publication:
- United States
- Language:
- English
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