Die Backside FIB Preparation for Identification and Characterization of Metal Voids
Both the increased complexity of integrated circuits, resulting in six or more levels of integration, and the increasing use of flip-chip packaging have driven the development of integrated circuit (IC) failure analysis tools that can be applied to the backside of the chip. Among these new approaches are focused ion beam (FIB) tools and processes for performing chip edits/repairs from the die backside. This paper describes the use of backside FIB for a failure analysis application rather than for chip repair. Specifically, they used FIB technology to prepare an IC for inspection of voided metal interconnects (lines) and vias. Conventional FIB milling was combined with a super-enhanced gas assisted milling process that uses XeF{sub 2} for rapid removal of large volumes of bulk silicon. This combined approach allowed removal of the TiW underlayer from a large number of Ml lines simultaneously, enabling rapid localization and plan view imaging of voids in lines and vias with backscattered electron (BSE) imaging in a scanning electron microscopy (SEM). Sequential cross sections of individual voided vias enabled them to develop a 3-d reconstruction of these voids. This information clarified how the voids were formed, helping to identify the IC process steps that needed to be changed.
- Research Organization:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Sandia National Lab. (SNL-CA), Livermore, CA (United States)
- Sponsoring Organization:
- US Department of Energy (US)
- DOE Contract Number:
- AC04-94AL85000
- OSTI ID:
- 9678
- Report Number(s):
- SAND99-1978C; TRN: AH200124%%372
- Resource Relation:
- Conference: International Symposium for Testing and Failure Analysis, Santa Clara, CA (US), 11/14/1999--11/18/1999; Other Information: PBD: 28 Jul 1999
- Country of Publication:
- United States
- Language:
- English
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