Dual-Side Wafer Processing and Resonant Tunneling Transistor Applications
We describe dual-side wafer processing and its application to resonant tunneling transistors in a planar configuration. The fabrication technique utilizes a novel flip-chip, wafer thinning process called epoxy-bond and stop-etch (EBASE) process, where the substrate material is removed by selective wet etching and stopped at an etch-stop layer. This EBASE method results in a semiconductor epitaxial layer that is typically less than a micron thick and has a mirror-finish, allowing backside gates to be placed in close proximity to frontside gates. Utilizing this technique, a resonant tunneling transistor--the double electron layer tunneling transistor (DELTT)--can be fabricated in a fully planar configuration, where the tunneling between two selectively-contacted 2DEGs in GaAs or InGaAs quantum wells is modulated by surface Schottky gate. Low temperature electrical characterization yields source-drain I-V curves with a gate-tunable negative differential resistance.
- Research Organization:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Sandia National Lab. (SNL-CA), Livermore, CA (United States)
- Sponsoring Organization:
- US Department of Energy (US)
- DOE Contract Number:
- AC04-94AL85000
- OSTI ID:
- 9577
- Report Number(s):
- SAND99-1419C; TRN: AH200124%%326
- Resource Relation:
- Conference: 1999 Joint International Meeting (SOTAPOCS XXXI), Honolulu, HI (US), 10/17/1999--10/22/1999; Other Information: PBD: 20 Jul 1999
- Country of Publication:
- United States
- Language:
- English
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