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Title: CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.

Abstract

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

Authors:
; ; ;
Publication Date:
Research Org.:
Sandia National Laboratories
Sponsoring Org.:
USDOE
OSTI Identifier:
947831
Report Number(s):
SAND2008-5487C
TRN: US200905%%195
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Conference
Resource Relation:
Conference: Proposed for presentation at the IEEE NANO 2008 Conference held August 18-21, 2008 in Arlington, TX.
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING; DESIGN; SILICON; TRANSISTORS; QUBITS; READOUT SYSTEMS

Citation Formats

Gurrieri, Thomas M, Lilly, Michael Patrick, Carroll, Malcolm S, and Levy, James E. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.. United States: N. p., 2008. Web.
Gurrieri, Thomas M, Lilly, Michael Patrick, Carroll, Malcolm S, & Levy, James E. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.. United States.
Gurrieri, Thomas M, Lilly, Michael Patrick, Carroll, Malcolm S, and Levy, James E. Fri . "CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.". United States.
@article{osti_947831,
title = {CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.},
author = {Gurrieri, Thomas M and Lilly, Michael Patrick and Carroll, Malcolm S and Levy, James E},
abstractNote = {Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2008},
month = {8}
}

Conference:
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