CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.

Conference · Fri Aug 01 00:00:00 EDT 2008

OSTI ID:947831

Gurrieri, Thomas M; Lilly, Michael Patrick; Carroll, Malcolm S; Levy, James E

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

• Research Organization: Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC04-94AL85000
• OSTI ID: 947831
• Report Number(s): SAND2008-5487C; TRN: US200905%%195
• Resource Relation: Conference: Proposed for presentation at the IEEE NANO 2008 Conference held August 18-21, 2008 in Arlington, TX.
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
DESIGN
SILICON
TRANSISTORS
QUBITS
READOUT SYSTEMS