MONOLITHIC ACTIVE PIXEL MATRIX WITH BINARY COUNTERS IN AN SOI PROCESS.
Conference
·
OSTI ID:909965
The design of a Prototype monolithic active pixel matrix, designed in a 0.15 {micro}m CMOS SOI Process, is presented. The process allowed connection between the electronics and the silicon volume under the layer of buried oxide (BOX). The small size vias traversing through the BOX and implantation of small p-type islands in the n-type bulk result in a monolithic imager. During the acquisition time, all pixels register individual radiation events incrementing the counters. The counting rate is up to 1 MHz per pixel. The contents of counters are shifted out during the readout phase. The designed prototype is an array of 64 x 64 pixels and the pixel size is 26 x 26 {micro}m{sup 2}.
- Research Organization:
- Brookhaven National Lab. (BNL), Upton, NY (United States)
- Sponsoring Organization:
- Doe - Office Of Science
- DOE Contract Number:
- DE-AC02-98CH10886
- OSTI ID:
- 909965
- Report Number(s):
- BNL-77972-2007-CP; R&D Project: 07032; KA-04-04; TRN: US200723%%304
- Resource Relation:
- Conference: 2007 INTERNATIONAL IMAGE SENSOR WORKSHOP; OGUNQUIT, ME; 20070607 through 20070610
- Country of Publication:
- United States
- Language:
- English
Similar Records
Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC
Monolithic active pixel matrix with binary counters (MAMBO III) ASIC
A vertically integrated pixel readout device for the Vertex Detector at the International Linear Collider
Conference
·
Mon Nov 01 00:00:00 EDT 2010
·
OSTI ID:909965
+1 more
Monolithic active pixel matrix with binary counters (MAMBO III) ASIC
Conference
·
Fri Jan 01 00:00:00 EST 2010
· PoS VERTEX2010:029,2010
·
OSTI ID:909965
+1 more
A vertically integrated pixel readout device for the Vertex Detector at the International Linear Collider
Journal Article
·
Mon Dec 01 00:00:00 EST 2008
· Submitted to IEEE Trans. on Electron Devices
·
OSTI ID:909965
+5 more