skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: PEP-II Transverse Feedback Electronics Upgrade

Abstract

The PEP-II B Factory at the Stanford Linear Accelerator Center (SLAC) requires an upgrade of the transverse feedback system electronics. The new electronics require 12-bit resolution and a minimum sampling rate of 238 Msps. A Field Programmable Gate Array (FPGA) is used to implement the feedback algorithm. The FPGA also contains an embedded PowerPC 405 (PPC-405) processor to run control system interface software for data retrieval, diagnostics, and system monitoring. The design of this system is based on the Xilinx(R) ML300 Development Platform, a circuit board set containing an FPGA with an embedded processor, a large memory bank, and other peripherals. This paper discusses the design of a digital feedback system based on an FPGA with an embedded processor. Discussion will include specifications, component selection, and integration with the ML300 design.

Authors:
; ; ;
Publication Date:
Research Org.:
Ernest Orlando Lawrence Berkeley NationalLaboratory, Berkeley, CA (US)
Sponsoring Org.:
USDOE Director. Office of Science. Office of High EnergyPhysics, Stanford Linear Accelerator
OSTI Identifier:
877628
Report Number(s):
LBNL-57565
R&D Project: R165; BnR: KA1202021; TRN: US0601627
DOE Contract Number:  
DE-AC02-05CH11231
Resource Type:
Conference
Resource Relation:
Conference: Particle Accelerator Conference 2005, Knoxville,TN, May 16-20, 2005
Country of Publication:
United States
Language:
English
Subject:
43 PARTICLE ACCELERATORS; 47 OTHER INSTRUMENTATION; ACCELERATORS; CONTROL SYSTEMS; DESIGN; FEEDBACK; MONITORING; RESOLUTION; SAMPLING; SPECIFICATIONS; STANFORD LINEAR ACCELERATOR CENTER; PEP-II transverse feedback embedded

Citation Formats

Weber, J., Chin, M., Doolittle, L., and Akre, R.. PEP-II Transverse Feedback Electronics Upgrade. United States: N. p., 2005. Web.
Weber, J., Chin, M., Doolittle, L., & Akre, R.. PEP-II Transverse Feedback Electronics Upgrade. United States.
Weber, J., Chin, M., Doolittle, L., and Akre, R.. Mon . "PEP-II Transverse Feedback Electronics Upgrade". United States. https://www.osti.gov/servlets/purl/877628.
@article{osti_877628,
title = {PEP-II Transverse Feedback Electronics Upgrade},
author = {Weber, J. and Chin, M. and Doolittle, L. and Akre, R.},
abstractNote = {The PEP-II B Factory at the Stanford Linear Accelerator Center (SLAC) requires an upgrade of the transverse feedback system electronics. The new electronics require 12-bit resolution and a minimum sampling rate of 238 Msps. A Field Programmable Gate Array (FPGA) is used to implement the feedback algorithm. The FPGA also contains an embedded PowerPC 405 (PPC-405) processor to run control system interface software for data retrieval, diagnostics, and system monitoring. The design of this system is based on the Xilinx(R) ML300 Development Platform, a circuit board set containing an FPGA with an embedded processor, a large memory bank, and other peripherals. This paper discusses the design of a digital feedback system based on an FPGA with an embedded processor. Discussion will include specifications, component selection, and integration with the ML300 design.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Mon May 09 00:00:00 EDT 2005},
month = {Mon May 09 00:00:00 EDT 2005}
}

Conference:
Other availability
Please see Document Availability for additional information on obtaining the full-text document. Library patrons may search WorldCat to identify libraries that hold this conference proceeding.

Save / Share: