Eliminating livelock by assigning the same priority state to each message that is inputted into a flushable routing system during N time intervals
Patent
·
OSTI ID:869628
- Los Alamos, NM
Livelock-free message routing is provided in a network of interconnected nodes that is flushable in time T. An input message processor generates sequences of at least N time intervals, each of duration T. An input register provides for receiving and holding each input message, where the message is assigned a priority state p during an nth one of the N time intervals. At each of the network nodes a message processor reads the assigned priority state and awards priority to messages with priority state (p-1) during an nth time interval and to messages with priority state p during an (n+1) th time interval. The messages that are awarded priority are output on an output path toward the addressed output message processor. Thus, no message remains in the network for a time longer than T.
- Research Organization:
- Los Alamos National Laboratory (LANL), Los Alamos, NM
- DOE Contract Number:
- W-7405-ENG-36
- Assignee:
- United States of America as represented by United States (Washington, DC)
- Patent Number(s):
- US 5369745
- OSTI ID:
- 869628
- Country of Publication:
- United States
- Language:
- English
Time-Stamp Approach to Store-and-Forward Deadlock Prevention
|
journal | January 1987 |
Architecture And Applications Of The HEP Multiprocessor Computer System
|
conference | July 1982 |
The chaos router: a practical application of randomization in network routing
|
journal | March 1991 |
Similar Records
Eliminating livelock by assigning the same priority state to each message that is input into a flushable routing system during N time intervals
Identifying messaging completion in a parallel computer by checking for change in message received and transmitted count at each node
Parallel processing network and method
Patent
·
1994
·
OSTI ID:6835530
Identifying messaging completion in a parallel computer by checking for change in message received and transmitted count at each node
Patent
·
2009
·
OSTI ID:988401
Parallel processing network and method
Patent
·
1988
·
OSTI ID:6337889
Related Subjects
/709/370/710/
addressed
assigned
assigning
awarded
duration
eliminating
flushable
generates
holding
input
inputted
interconnected
interval
intervals
livelock
livelock-free
message
message routing
messages
network
nodes
nth
output
p-1
path
priority
processor
processor generates
provided
provides
reads
receiving
register
remains
routing
sequences
time
time interval
time intervals
addressed
assigned
assigning
awarded
duration
eliminating
flushable
generates
holding
input
inputted
interconnected
interval
intervals
livelock
livelock-free
message
message routing
messages
network
nodes
nth
output
p-1
path
priority
processor
processor generates
provided
provides
reads
receiving
register
remains
routing
sequences
time
time interval
time intervals