System for routing messages in a vertex symmetric network by using addresses formed from permutations of the transmission line indicees
- Los Alamos, NM
A network of interconnected processors is formed from a vertex symmetric graph selected from graphs .GAMMA..sub.d (k) with degree d, diameter k, and (d+1)!/(d-k+1)! processors for each d.gtoreq.k and .GAMMA..sub.d (k,-1) with degree 3-1, diameter k+1, and (d+1)!/(d-k+1)! processors for each d.gtoreq.k.gtoreq.4. Each processor has an address formed by one of the permutations from a predetermined sequence of letters chosen a selected number of letters at a time, and an extended address formed by appending to the address the remaining ones of the predetermined sequence of letters. A plurality of transmission channels is provided from each of the processors, where each processor has one less channel than the selected number of letters forming the sequence. Where a network .GAMMA..sub.d (k,-1) is provided, no processor has a channel connected to form an edge in a direction .delta..sub.1. Each of the channels has an identification number selected from the sequence of letters and connected from a first processor having a first extended address to a second processor having a second address formed from a second extended address defined by moving to the front of the first extended address the letter found in the position within the first extended address defined by the channel identification number. The second address is then formed by selecting the first elements of the second extended address corresponding to the selected number used to form the address permutations.
- Research Organization:
- Los Alamos National Laboratory (LANL), Los Alamos, NM (United States)
- DOE Contract Number:
- W-7405-ENG-36
- Assignee:
- United States of America as represented by Department of Energy (Washington, DC)
- Patent Number(s):
- US 5125076
- OSTI ID:
- 868362
- Country of Publication:
- United States
- Language:
- English
Vertex-transitive graphs
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journal | October 1964 |
A group-theoretic model for symmetric interconnection networks
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journal | April 1989 |
Strategies for interconnection networks: Some methods from graph theory
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journal | December 1986 |
A Design for Directed Graphs with Minimum Diameter
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journal | August 1983 |
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
|
journal | May 1987 |
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Related Subjects
messages
vertex
symmetric
network
addresses
formed
permutations
transmission
line
indicees
interconnected
processors
graph
selected
graphs
gamma
degree
diameter
d-k
gtoreq
-1
3-1
processor
address
predetermined
sequence
letters
chosen
time
extended
appending
remaining
ones
plurality
channels
provided
channel
forming
connected
form
edge
direction
delta
identification
defined
moving
front
letter
found
position
selecting
elements
corresponding
predetermined sequence
transmission line
vertex symmetric
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