Method of making high breakdown voltage semiconductor device

Patent · Mon Jan 01 00:00:00 EST 1990

OSTI ID:867396

Arthur, Stephen D ^[1]; Temple, Victor A. K. ^[2]

---

1. Scotia, NY
2. Jonesville, NY

A semiconductor device having at least one P-N junction and a multiple-zone junction termination extension (JTE) region which uniformly merges with the reverse blocking junction is disclosed. The blocking junction is graded into multiple zones of lower concentration dopant adjacent termination to facilitate merging of the JTE to the blocking junction and placing of the JTE at or near the high field point of the blocking junction. Preferably, the JTE region substantially overlaps the graded blocking junction region. A novel device fabrication method is also provided which eliminates the prior art step of separately diffusing the JTE region.

• DOE Contract Number: AC07-84NV10418
• Assignee: General Electric Company (Schenectady, NY)
• Patent Number(s): US 4927772
• OSTI ID: 867396
• Country of Publication: United States
• Language: English

Related Subjects

method
breakdown
voltage
semiconductor
device
p-n
junction
multiple-zone
termination
extension
jte
region
uniformly
merges
reverse
blocking
disclosed
graded
multiple
zones
concentration
dopant
adjacent
facilitate
merging
placing
near
field
preferably
substantially
overlaps
novel
fabrication
provided
eliminates
prior
step
separately
diffusing
device fabrication
fabrication method
p-n junction
breakdown voltage
semiconductor device
multiple zones
novel device
multiple zone
substantially overlap
junction region
/438/