skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Method for sputtering a PIN amorphous silicon semi-conductor device having partially crystallized P and N-layers

Abstract

A high efficiency amorphous silicon PIN semiconductor device having partially crystallized (microcrystalline) P and N layers is constructed by the sequential sputtering of N, I and P layers and at least one semi-transparent ohmic electrode. The method of construction produces a PIN device, exhibiting enhanced electrical and optical properties, improved physical integrity, and facilitates the preparation in a singular vacuum system and vacuum pump down procedure.

Inventors:
 [1];  [1]
  1. (Annandale, NJ)
Publication Date:
Research Org.:
Solar Energy Research Institute
OSTI Identifier:
865508
Patent Number(s):
US 4528082
Application Number:
06/535,901
Assignee:
Exxon Research and Engineering Co. (Florham Park, NJ) OSTI
DOE Contract Number:  
XZ-0-9219
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
method; sputtering; amorphous; silicon; semi-conductor; device; partially; crystallized; n-layers; efficiency; semiconductor; microcrystalline; layers; constructed; sequential; semi-transparent; ohmic; electrode; construction; produces; exhibiting; enhanced; electrical; optical; properties; improved; physical; integrity; facilitates; preparation; singular; vacuum; pump; procedure; amorphous silicon; semiconductor device; optical properties; vacuum pump; semi-conductor device; semi-transparent ohmic; ohmic electrode; enhanced electrical; improved physical; sequential sputtering; silicon semi-conductor; partially crystallized; exhibiting enhanced; transparent ohmic; efficiency amorphous; /204/136/257/

Citation Formats

Moustakas, Theodore D., and Maruska, H. Paul. Method for sputtering a PIN amorphous silicon semi-conductor device having partially crystallized P and N-layers. United States: N. p., 1985. Web.
Moustakas, Theodore D., & Maruska, H. Paul. Method for sputtering a PIN amorphous silicon semi-conductor device having partially crystallized P and N-layers. United States.
Moustakas, Theodore D., and Maruska, H. Paul. Tue . "Method for sputtering a PIN amorphous silicon semi-conductor device having partially crystallized P and N-layers". United States. https://www.osti.gov/servlets/purl/865508.
@article{osti_865508,
title = {Method for sputtering a PIN amorphous silicon semi-conductor device having partially crystallized P and N-layers},
author = {Moustakas, Theodore D. and Maruska, H. Paul},
abstractNote = {A high efficiency amorphous silicon PIN semiconductor device having partially crystallized (microcrystalline) P and N layers is constructed by the sequential sputtering of N, I and P layers and at least one semi-transparent ohmic electrode. The method of construction produces a PIN device, exhibiting enhanced electrical and optical properties, improved physical integrity, and facilitates the preparation in a singular vacuum system and vacuum pump down procedure.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1985},
month = {7}
}

Patent:

Save / Share: