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U.S. Department of Energy
Office of Scientific and Technical Information

Clock distribution system for digital computers

Patent ·
OSTI ID:863816
Apparatus for eliminating, in each clock distribution amplifier of a clock distribution system, sequential pulse catch-up error due to one pulse "overtaking" a prior clock pulse. The apparatus includes timing means to produce a periodic electromagnetic signal with a fundamental frequency having a fundamental frequency component V'.sub.01 (t); an array of N signal characteristic detector means, with detector means No. 1 receiving the timing means signal and producing a change-of-state signal V.sub.1 (t) in response to receipt of a signal above a predetermined threshold; N substantially identical filter means, one filter means being operatively associated with each detector means, for receiving the change-of-state signal V.sub.n (t) and producing a modified change-of-state signal V'.sub.n (t) (n=1, . . . , N) having a fundamental frequency component that is substantially proportional to V'.sub.01 (t-.theta..sub.n (t) with a cumulative phase shift .theta..sub.n (t) having a time derivative that may be made uniformly and arbitrarily small; and with the detector means n+1 (1.ltoreq.n
Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA
DOE Contract Number:
W-7405-ENG-48
Assignee:
United States of America as represented by United States (Washington, DC)
Patent Number(s):
US 4253065
OSTI ID:
863816
Country of Publication:
United States
Language:
English