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Title: A Low-Power VHDL Design for an Elliptic Curve Digital Signature Chip

Abstract

The authors present a VHDL design that incorporates optimizations intended to provide digital signature generation with as little power, space, and time as possible. These three primary objectives of power, size, and speed must be balanced along with other important goals, including flexibility of the hardware and ease of use. The highest-level function doffered by their hardware design is Elliptic Curve Optimal El Gamal digital signature generation. The parameters are defined over the finite field GF(2{sup 178}), which gives security that is roughly equivalent to that provided by 1500-bit RSA signatures. The optimizations include using the point-halving algorithm for elliptic curves, field towers to speed up the finite field arithmetic in general, and further enhancements of basic finite field arithmetic operations. The result is a synthesized VHDL digital signature design (using a CMOS 0.5{micro}m, 5V, 25 C library) of 191,000 gates that generates a signature in 4.4 ms at 20 MHz.

Authors:
; ; ; ;
Publication Date:
Research Org.:
Sandia National Labs., Albuquerque, NM (US); Sandia National Labs., Livermore, CA (US)
Sponsoring Org.:
US Department of Energy (US)
OSTI Identifier:
802030
Report Number(s):
SAND2002-3194
TRN: US200223%%443
DOE Contract Number:
AC04-94AL85000
Resource Type:
Technical Report
Resource Relation:
Other Information: PBD: 1 Sep 2002
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; ALGORITHMS; DESIGN; FLEXIBILITY; SECURITY; IDENTIFICATION SYSTEMS; SIZE; ENERGY CONSERVATION; COMPUTERS

Citation Formats

SCHROEPPEL, RICHARD C., BEAVER, CHERYL L., DRAELOS, TIMOTHY J., GONZALES, RITA A., and MILLER, RUSSELL D.. A Low-Power VHDL Design for an Elliptic Curve Digital Signature Chip. United States: N. p., 2002. Web. doi:10.2172/802030.
SCHROEPPEL, RICHARD C., BEAVER, CHERYL L., DRAELOS, TIMOTHY J., GONZALES, RITA A., & MILLER, RUSSELL D.. A Low-Power VHDL Design for an Elliptic Curve Digital Signature Chip. United States. doi:10.2172/802030.
SCHROEPPEL, RICHARD C., BEAVER, CHERYL L., DRAELOS, TIMOTHY J., GONZALES, RITA A., and MILLER, RUSSELL D.. Sun . "A Low-Power VHDL Design for an Elliptic Curve Digital Signature Chip". United States. doi:10.2172/802030. https://www.osti.gov/servlets/purl/802030.
@article{osti_802030,
title = {A Low-Power VHDL Design for an Elliptic Curve Digital Signature Chip},
author = {SCHROEPPEL, RICHARD C. and BEAVER, CHERYL L. and DRAELOS, TIMOTHY J. and GONZALES, RITA A. and MILLER, RUSSELL D.},
abstractNote = {The authors present a VHDL design that incorporates optimizations intended to provide digital signature generation with as little power, space, and time as possible. These three primary objectives of power, size, and speed must be balanced along with other important goals, including flexibility of the hardware and ease of use. The highest-level function doffered by their hardware design is Elliptic Curve Optimal El Gamal digital signature generation. The parameters are defined over the finite field GF(2{sup 178}), which gives security that is roughly equivalent to that provided by 1500-bit RSA signatures. The optimizations include using the point-halving algorithm for elliptic curves, field towers to speed up the finite field arithmetic in general, and further enhancements of basic finite field arithmetic operations. The result is a synthesized VHDL digital signature design (using a CMOS 0.5{micro}m, 5V, 25 C library) of 191,000 gates that generates a signature in 4.4 ms at 20 MHz.},
doi = {10.2172/802030},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Sun Sep 01 00:00:00 EDT 2002},
month = {Sun Sep 01 00:00:00 EDT 2002}
}

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