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Title: Radiation-hard CMOS/SOS standard cell circuits

Abstract

A new multiport silicon-gate, CMOS/SOS standard cell family that achieves transient upset and total dose hardness has been designed and evaluated. This radiation hardness was achieved by design and process procedures normally not considered in conventional CMOS/SOS circuits. To evaluate the cell family a test chip and arithmetic logic unit (ALU) integrated circuits were fabricated. The cell-family performance was characterized utilizing 60ns to 1..mu..s electron pulses from the LINAC and total dose gamma irradiation from the cobalt-60 source. The results show circuit upset at levels greater than 10/sup 11/ rad (Si)/s for short (60ns) irradiation pulses. Total dose irradiations to 10/sup 6/ rad (Si) indicate a 20 percent reduction in circuit speed and a factor of 10 increase in chip leakage. Utilizing these standard cell building blocks, radiation hard, quick-turnaround, low-cost custom LSI arrays can be fabricated using design automation techniques.

Authors:
 [1];
  1. Naval Research Lab., Washington, DC
Publication Date:
OSTI Identifier:
7213067
Resource Type:
Conference
Journal Name:
IEEE Trans. Nucl. Sci.; (United States)
Additional Journal Information:
Journal Volume: NS-23:6; Conference: IEEE annual conference on nuclear and space radiation effects, San Diego, CA, USA, 27 Jul 1976
Country of Publication:
United States
Language:
English
Subject:
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY; INTEGRATED CIRCUITS; RADIATION HARDENING; DESIGN; FABRICATION; LEAKAGE CURRENT; LOGIC CIRCUITS; MOS TRANSISTORS; TESTING; CURRENTS; ELECTRIC CURRENTS; ELECTRONIC CIRCUITS; HARDENING; MICROELECTRONIC CIRCUITS; PHYSICAL RADIATION EFFECTS; RADIATION EFFECTS; SEMICONDUCTOR DEVICES; TRANSISTORS; 440200* - Radiation Effects on Instrument Components, Instruments, or Electronic Systems

Citation Formats

Palkuti, L J, and Pryor, R. Radiation-hard CMOS/SOS standard cell circuits. United States: N. p., 1976. Web.
Palkuti, L J, & Pryor, R. Radiation-hard CMOS/SOS standard cell circuits. United States.
Palkuti, L J, and Pryor, R. Wed . "Radiation-hard CMOS/SOS standard cell circuits". United States.
@article{osti_7213067,
title = {Radiation-hard CMOS/SOS standard cell circuits},
author = {Palkuti, L J and Pryor, R},
abstractNote = {A new multiport silicon-gate, CMOS/SOS standard cell family that achieves transient upset and total dose hardness has been designed and evaluated. This radiation hardness was achieved by design and process procedures normally not considered in conventional CMOS/SOS circuits. To evaluate the cell family a test chip and arithmetic logic unit (ALU) integrated circuits were fabricated. The cell-family performance was characterized utilizing 60ns to 1..mu..s electron pulses from the LINAC and total dose gamma irradiation from the cobalt-60 source. The results show circuit upset at levels greater than 10/sup 11/ rad (Si)/s for short (60ns) irradiation pulses. Total dose irradiations to 10/sup 6/ rad (Si) indicate a 20 percent reduction in circuit speed and a factor of 10 increase in chip leakage. Utilizing these standard cell building blocks, radiation hard, quick-turnaround, low-cost custom LSI arrays can be fabricated using design automation techniques.},
doi = {},
journal = {IEEE Trans. Nucl. Sci.; (United States)},
number = ,
volume = NS-23:6,
place = {United States},
year = {1976},
month = {12}
}

Conference:
Other availability
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