Floating-point systolic array including serial processors
This patent describes, in a systolic array system utilizing a plurality of semiconductor chips, a semiconductor chip. It comprises: a plurality of processing elements each including a floating-point serial processor and a plurality of data storage registers; global bus means coupled to the serial processor of each of the plurality of processing elements for inputing and outputing data to and from each chip and for programming each serial processor; and a plurality of data buses coupled to each of the plurality of data storage registers of each of the plurality of processing elements. The global bus means being coupled to the plurality of data storage registers for programming the data storage registers.
- Assignee:
- Motorola, Inc., Schaumburg, IL
- Patent Number(s):
- US 4872133
- Application Number:
- PPN: US 7157682A
- OSTI ID:
- 7129241
- Resource Relation:
- Patent File Date: 18 Feb 1988
- Country of Publication:
- United States
- Language:
- English
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