Performance study of a clustered shared-memory multiprocessor

Thesis/Dissertation · Fri Jan 01 00:00:00 EST 1988

OSTI ID:7129052

Naji, A R

A shared-memory multiprocessor having clusters of processing elements and memory modules is proposed. Since the delay through a multistage interconnection network, which increases logarithmically, can be large when the number of processors is large, clustering helps reduce the average delay to access a memory module. Each cluster has two others as its neighbors. The clusters are interconnected in such a way that the memory modules of a cluster can also be accessed by the processors of the neighboring clusters besides its own processors via its interconnection network. The coupling between the clusters provides flexibility for the scheduling of tasks. The processors and memory modules of all clusters are also connected to a shared interconnection network allowing the processors to access memory modules of the nonneighboring clusters. A Markov-chain model is developed for the circuit-switching strategy, and queueing models are used for the packet-switching strategy. The circuit-switching model is extended to include synchronized memory accesses. Sharing of network ports by the processors is also considered. A scheduling algorithm is proposed to assign tasks from directed acyclic task graphs to processors using 0-1 integer programming and a lookahead technique.

• Research Organization: Michigan Univ., Ann Arbor, MI (USA)
• OSTI ID: 7129052
• Resource Relation: Other Information: Thesis (Ph. D.)
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
MEMORY MANAGEMENT
TASK SCHEDULING
MARKOV PROCESS
MEMORY DEVICES
PROGRAMMING
QUEUES
SWITCHING CIRCUITS
DATA PROCESSING
ELECTRONIC CIRCUITS
PROCESSING
STOCHASTIC PROCESSES
990200* - Mathematics & Computers