SLS complementary logic devices with increase carrier mobility
In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated. 5 figures.
- DOE Contract Number:
- AC04-76DP00789
- Assignee:
- Sandia Corporation, Albuquerque, NM (United States)
- Patent Number(s):
- A; US 5031007
- Application Number:
- PPN: US 7-604399
- OSTI ID:
- 7083838
- Country of Publication:
- United States
- Language:
- English
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