A VMEbus clock system for accelerator control
- Fermi National Accelerator Lab., Batavia, IL (US)
Because an accelerator has many systems which must operate with a high degree of synchronization, a clock signal is typically generated which carries timing information to the various accelerator components. This paper discusses two VMEbus modules designed to generate and receive this clock signal. Together they implement a clock system which can generate timing markers with 200 nanosecond resolution and can generate timing delays of over one hour with one microsecond resolution. The Clock Generator module contains both a time line generator programmed to produce clock events at specific times and eight programmable input channels to produce clock events when externally triggered. Additional clock events are generated directly from the VMEbus. Generators can be cascaded for added capability. The Clock Timer module receives the signal from the generator. It can be programmed to recognize specific clock events which act as triggers to the eight timing channels on the module. Each timing channel is programmed with a 32-bit delay value. The channels are clocked at 1 MHz. At the end of the delay period, a timer channel produces an output pulse and optionally can generate a bus interrupt.
- OSTI ID:
- 7068521
- Report Number(s):
- CONF-9106122-; CODEN: IETNA
- Journal Information:
- IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States), Vol. 39:2; Conference: 7. international conference on real time computer applications in nuclear, particle and plasma physics, Juelich (Germany), 18-28 Jun 1991; ISSN 0018-9499
- Country of Publication:
- United States
- Language:
- English
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99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
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DATA ACQUISITION SYSTEMS
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SYNCHRONIZATION
TIME RESOLUTION
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990200 - Mathematics & Computers