A flexible 128 channel silicon strip detector instrumentation integrated circuit with sparse data readout
A new full custom CMOS integrated circuit for silicon strip detector systems has been design, fabricated and tested. The I.C. contains 128 parallel data acquisition channels and considerable peripheral circuitry. Each channel consists of a low noise, low power charge sensitive amplifier, a multi-stage auto-balanced comparator, an analog multiplexer, nearest neighbor logic, priority search logic and a share of a position encoding read-only memory. The analog system can subtract both detector pedestal and leakage current on a channel by channel basis. A key feature of this design is the inclusion of on-chip sparse read-out circuitry, which allows efficient management of low occupancy events. Designed for use at the Collider Detector Facility (CDF) at Fermilab, it is suitable for large scale silicon detector systems where a large, dense array of fast, low power electronics is required.
- Research Organization:
- Lawrence Berkeley Lab., Berkeley, CA (US)
- OSTI ID:
- 7029599
- Report Number(s):
- CONF-871006-; TRN: 88-025710
- Journal Information:
- IEEE Trans. Nucl. Sci.; (United States), Vol. 35:1; Conference: 34. nuclear science symposium and 19. nuclear power systems symposium, San Francisco, CA, USA, 21 Oct 1987
- Country of Publication:
- United States
- Language:
- English
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