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Title: Multi-processor including data flow accelerator module

Abstract

This patent describes a data flow computer for implementing a data flow graph. The computer including a plurality of processing means, each operable for executing a primitive computation of a node of the graph, and accelerator means for accelerating execution of the computation. The accelerator means comprising: a plurality of memory cells for representing, respectively, each of the nodes of the graph, each memory cell including: a plurality of slot means for storing all the data operands required for a primitive computation; and indicating means for providing a first output upon conclusion of each memory cycle for indicating that all operands required by a primitive associated with the cell are available; and identifying means for storing the address of each memory cell with an indicating means providing a first output.

Inventors:
;
Publication Date:
OSTI Identifier:
6937980
Patent Number(s):
US 4893234; A
Application Number:
PPN: US 7-003540A
Assignee:
Dept. of Energy, Washington, DC
Resource Type:
Patent
Resource Relation:
Patent File Date: 15 Jan 1987
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; COMPUTERS; DATA-FLOW PROCESSING; COMPUTER ARCHITECTURE; COMPUTER GRAPHICS; MEMORY DEVICES; PROGRAMMING; 990200* - Mathematics & Computers

Citation Formats

Davidson, G S, and Pierce, P E. Multi-processor including data flow accelerator module. United States: N. p., 1990. Web.
Davidson, G S, & Pierce, P E. Multi-processor including data flow accelerator module. United States.
Davidson, G S, and Pierce, P E. 1990. "Multi-processor including data flow accelerator module". United States.
@article{osti_6937980,
title = {Multi-processor including data flow accelerator module},
author = {Davidson, G S and Pierce, P E},
abstractNote = {This patent describes a data flow computer for implementing a data flow graph. The computer including a plurality of processing means, each operable for executing a primitive computation of a node of the graph, and accelerator means for accelerating execution of the computation. The accelerator means comprising: a plurality of memory cells for representing, respectively, each of the nodes of the graph, each memory cell including: a plurality of slot means for storing all the data operands required for a primitive computation; and indicating means for providing a first output upon conclusion of each memory cycle for indicating that all operands required by a primitive associated with the cell are available; and identifying means for storing the address of each memory cell with an indicating means providing a first output.},
doi = {},
url = {https://www.osti.gov/biblio/6937980}, journal = {},
number = ,
volume = ,
place = {United States},
year = {1990},
month = {1}
}