Logical data skewing schemes for interleaved memories in vector processors

Sohi, G S

Title: Logical data skewing schemes for interleaved memories in vector processors

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Abstract

Sustained memory bandwidth for range of strides is a key to high-performance vector processing. To reduce the number of memory bank conflicts and thereby increase memory bandwidth, one often resorts to data skewing schemes. In this paper, the authors present a family of data skewing schemes called logical skewing schemes. In logical skewing schemes, the location of a data element is determined solely by logical manipulation of the address bits. The authors' experiments show that logical skewing schemes allow for better vector memory system performance than other known data skewing schemes without the significant increase in memory latency that is traditionally associated with data skewing schemes.

Authors:: Sohi, G S

Publication Date:: Fri Jan 01 00:00:00 EST 1988

OSTI Identifier:: 6933049

Resource Type:: Book

Country of Publication:: United States

Language:: English

Subject:: 99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; MEMORY DEVICES; FREQUENCY ANALYSIS; SUPERCOMPUTERS; ALGORITHMS; VECTOR PROCESSING; COMPUTERS; DIGITAL COMPUTERS; MATHEMATICAL LOGIC; PROGRAMMING; 990210* - Supercomputers- (1987-1989)

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                    Sohi, G S. Logical data skewing schemes for interleaved memories in vector processors.  United States: N. p., 1988. 
        Web.

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                    Sohi, G S. Logical data skewing schemes for interleaved memories in vector processors.  United States.

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                    Sohi, G S. 1988.  
        "Logical data skewing schemes for interleaved memories in vector processors".  United States.

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@article{osti_6933049,

  title        = {Logical data skewing schemes for interleaved memories in vector processors},

  author       = {Sohi, G S},

  abstractNote = {Sustained memory bandwidth for range of strides is a key to high-performance vector processing. To reduce the number of memory bank conflicts and thereby increase memory bandwidth, one often resorts to data skewing schemes. In this paper, the authors present a family of data skewing schemes called logical skewing schemes. In logical skewing schemes, the location of a data element is determined solely by logical manipulation of the address bits. The authors' experiments show that logical skewing schemes allow for better vector memory system performance than other known data skewing schemes without the significant increase in memory latency that is traditionally associated with data skewing schemes.},

  doi          = {},

  url          = {https://www.osti.gov/biblio/6933049},
  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Fri Jan 01 00:00:00 EST 1988},

  month        = {Fri Jan 01 00:00:00 EST 1988}

}

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