Poor man's gate arrays logic cell arrays

Conference · Mon Feb 01 00:00:00 EST 1988 · IEEE Trans. Nucl. Sci.; (United States)

OSTI ID:6930289

Brandenburg, G; Gorschutz, U; Muller, K D

For simple applications, where gate arrays are too expensive and the turn around time for design, production and changes is not acceptable, logic cell arrays (LCA) provide an interesting alternative. Logic cell arrays store the gate interconnecting information in on-chip memory cells and can therefore be loaded or reloaded within several milliseconds. As an example, the design of an interface for a neutron time of flight multidetector arrangement is described and advantages and disadvantages of the approach are discussed.

• Research Organization: Zentrallabor fur Elektronik, Kernforschungsanlage Julich GmbH, Postfach 1913, 5170 Julich (DE)
• OSTI ID: 6930289
• Report Number(s): CONF-871006-
• Journal Information: IEEE Trans. Nucl. Sci.; (United States), Vol. 35:1; Conference: 34. nuclear science symposium and 19. nuclear power systems symposium, San Francisco, CA, USA, 21 Oct 1987
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
MEMORY DEVICES
DEMONSTRATION PROGRAMS
DESIGN
990210* - Supercomputers- (1987-1989)